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https://github.com/RPCS3/llvm-mirror.git
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4c1f3c24db
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
138 lines
3.0 KiB
C++
138 lines
3.0 KiB
C++
//===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in
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// the LLVM NVPTX back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_NVPTX_H
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#define LLVM_TARGET_NVPTX_H
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#include "MCTargetDesc/NVPTXBaseInfo.h"
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#include "llvm/IR/Module.h"
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#include "llvm/IR/Value.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cassert>
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#include <iosfwd>
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namespace llvm {
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class NVPTXTargetMachine;
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class FunctionPass;
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class formatted_raw_ostream;
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namespace NVPTXCC {
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enum CondCodes {
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EQ,
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NE,
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LT,
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LE,
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GT,
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GE
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};
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}
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inline static const char *NVPTXCondCodeToString(NVPTXCC::CondCodes CC) {
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switch (CC) {
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case NVPTXCC::NE: return "ne";
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case NVPTXCC::EQ: return "eq";
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case NVPTXCC::LT: return "lt";
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case NVPTXCC::LE: return "le";
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case NVPTXCC::GT: return "gt";
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case NVPTXCC::GE: return "ge";
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}
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llvm_unreachable("Unknown condition code");
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}
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FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,
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llvm::CodeGenOpt::Level OptLevel);
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FunctionPass *createVectorElementizePass(NVPTXTargetMachine &);
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FunctionPass *createLowerStructArgsPass(NVPTXTargetMachine &);
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FunctionPass *createNVPTXReMatPass(NVPTXTargetMachine &);
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FunctionPass *createNVPTXReMatBlockPass(NVPTXTargetMachine &);
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bool isImageOrSamplerVal(const Value *, const Module *);
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extern Target TheNVPTXTarget32;
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extern Target TheNVPTXTarget64;
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namespace NVPTX
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{
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enum DrvInterface {
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NVCL,
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CUDA,
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TEST
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};
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// A field inside TSFlags needs a shift and a mask. The usage is
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// always as follows :
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// ((TSFlags & fieldMask) >> fieldShift)
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// The enum keeps the mask, the shift, and all valid values of the
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// field in one place.
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enum VecInstType {
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VecInstTypeShift = 0,
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VecInstTypeMask = 0xF,
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VecNOP = 0,
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VecLoad = 1,
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VecStore = 2,
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VecBuild = 3,
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VecShuffle = 4,
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VecExtract = 5,
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VecInsert = 6,
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VecDest = 7,
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VecOther = 15
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};
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enum SimpleMove {
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SimpleMoveMask = 0x10,
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SimpleMoveShift = 4
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};
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enum LoadStore {
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isLoadMask = 0x20,
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isLoadShift = 5,
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isStoreMask = 0x40,
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isStoreShift = 6
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};
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namespace PTXLdStInstCode {
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enum AddressSpace{
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GENERIC = 0,
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GLOBAL = 1,
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CONSTANT = 2,
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SHARED = 3,
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PARAM = 4,
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LOCAL = 5
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};
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enum FromType {
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Unsigned = 0,
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Signed,
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Float
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};
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enum VecType {
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Scalar = 1,
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V2 = 2,
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V4 = 4
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};
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}
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}
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} // end namespace llvm;
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// Defines symbolic names for NVPTX registers. This defines a mapping from
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// register name to register number.
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#define GET_REGINFO_ENUM
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#include "NVPTXGenRegisterInfo.inc"
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// Defines symbolic names for the NVPTX instructions.
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#define GET_INSTRINFO_ENUM
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#include "NVPTXGenInstrInfo.inc"
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#endif
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