mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 03:33:20 +01:00
702277f07f
Replace spills to memory with spills to registers, if possible. This applies mostly to predicate registers (both scalar and vector), since they are very limited in number. A spill of a predicate register may happen even if there is a general-purpose register available. In cases like this the stack spill/reload may be eliminated completely. This optimization will consider all stack objects, regardless of where they came from and try to match the live range of the stack slot with a dead range of a register from an appropriate register class. llvm-svn: 260758
64 lines
1.8 KiB
CMake
64 lines
1.8 KiB
CMake
set(LLVM_TARGET_DEFINITIONS Hexagon.td)
|
|
|
|
tablegen(LLVM HexagonGenAsmMatcher.inc -gen-asm-matcher)
|
|
tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
|
|
tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
|
|
tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
|
|
tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer)
|
|
tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
|
|
tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
|
|
tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
|
|
tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
|
|
tablegen(LLVM HexagonGenSubtargetInfo.inc -gen-subtarget)
|
|
add_public_tablegen_target(HexagonCommonTableGen)
|
|
|
|
add_llvm_target(HexagonCodeGen
|
|
BitTracker.cpp
|
|
HexagonAsmPrinter.cpp
|
|
HexagonBitSimplify.cpp
|
|
HexagonBitTracker.cpp
|
|
HexagonBlockRanges.cpp
|
|
HexagonCFGOptimizer.cpp
|
|
HexagonCommonGEP.cpp
|
|
HexagonCopyToCombine.cpp
|
|
HexagonEarlyIfConv.cpp
|
|
HexagonExpandCondsets.cpp
|
|
HexagonFixupHwLoops.cpp
|
|
HexagonFrameLowering.cpp
|
|
HexagonGenExtract.cpp
|
|
HexagonGenInsert.cpp
|
|
HexagonGenMux.cpp
|
|
HexagonGenPredicate.cpp
|
|
HexagonHardwareLoops.cpp
|
|
HexagonInstrInfo.cpp
|
|
HexagonISelDAGToDAG.cpp
|
|
HexagonISelLowering.cpp
|
|
HexagonMachineFunctionInfo.cpp
|
|
HexagonMachineScheduler.cpp
|
|
HexagonMCInstLower.cpp
|
|
HexagonNewValueJump.cpp
|
|
HexagonOptimizeSZextends.cpp
|
|
HexagonPeephole.cpp
|
|
HexagonRDF.cpp
|
|
HexagonRDFOpt.cpp
|
|
HexagonRegisterInfo.cpp
|
|
HexagonSelectionDAGInfo.cpp
|
|
HexagonSplitConst32AndConst64.cpp
|
|
HexagonSplitDouble.cpp
|
|
HexagonStoreWidening.cpp
|
|
HexagonSubtarget.cpp
|
|
HexagonTargetMachine.cpp
|
|
HexagonTargetObjectFile.cpp
|
|
HexagonTargetTransformInfo.cpp
|
|
HexagonVLIWPacketizer.cpp
|
|
RDFCopy.cpp
|
|
RDFDeadCode.cpp
|
|
RDFGraph.cpp
|
|
RDFLiveness.cpp
|
|
)
|
|
|
|
add_subdirectory(AsmParser)
|
|
add_subdirectory(TargetInfo)
|
|
add_subdirectory(MCTargetDesc)
|
|
add_subdirectory(Disassembler)
|