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https://github.com/RPCS3/llvm-mirror.git
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dd9f94c292
An interplay of code from D70210, along with code from the Value-Numbering-esque hash-based namer from D70210, as well as some crusty code from the original MIR-Canon code lead to multiple causes of failure when canonicalizing or renaming vregs for MIR with multiple basic blocks. This patch fixes those issues while deleting some no longer needed code and adding a nice diamond test case to boot. Differential Revision: https://reviews.llvm.org/D70478
437 lines
12 KiB
C++
437 lines
12 KiB
C++
//===-------------- MIRCanonicalizer.cpp - MIR Canonicalizer --------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The purpose of this pass is to employ a canonical code transformation so
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// that code compiled with slightly different IR passes can be diffed more
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// effectively than otherwise. This is done by renaming vregs in a given
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// LiveRange in a canonical way. This pass also does a pseudo-scheduling to
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// move defs closer to their use inorder to reduce diffs caused by slightly
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// different schedules.
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//
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// Basic Usage:
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//
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// llc -o - -run-pass mir-canonicalizer example.mir
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//
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// Reorders instructions canonically.
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// Renames virtual register operands canonically.
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// Strips certain MIR artifacts (optionally).
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//
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//===----------------------------------------------------------------------===//
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#include "MIRVRegNamerUtils.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <queue>
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using namespace llvm;
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namespace llvm {
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extern char &MIRCanonicalizerID;
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} // namespace llvm
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#define DEBUG_TYPE "mir-canonicalizer"
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static cl::opt<unsigned>
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CanonicalizeFunctionNumber("canon-nth-function", cl::Hidden, cl::init(~0u),
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cl::value_desc("N"),
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cl::desc("Function number to canonicalize."));
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namespace {
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class MIRCanonicalizer : public MachineFunctionPass {
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public:
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static char ID;
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MIRCanonicalizer() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override {
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return "Rename register operands in a canonical ordering.";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // end anonymous namespace
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char MIRCanonicalizer::ID;
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char &llvm::MIRCanonicalizerID = MIRCanonicalizer::ID;
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INITIALIZE_PASS_BEGIN(MIRCanonicalizer, "mir-canonicalizer",
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"Rename Register Operands Canonically", false, false)
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INITIALIZE_PASS_END(MIRCanonicalizer, "mir-canonicalizer",
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"Rename Register Operands Canonically", false, false)
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static std::vector<MachineBasicBlock *> GetRPOList(MachineFunction &MF) {
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if (MF.empty())
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return {};
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ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin());
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std::vector<MachineBasicBlock *> RPOList;
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for (auto MBB : RPOT) {
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RPOList.push_back(MBB);
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}
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return RPOList;
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}
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static bool
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rescheduleLexographically(std::vector<MachineInstr *> instructions,
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MachineBasicBlock *MBB,
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std::function<MachineBasicBlock::iterator()> getPos) {
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bool Changed = false;
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using StringInstrPair = std::pair<std::string, MachineInstr *>;
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std::vector<StringInstrPair> StringInstrMap;
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for (auto *II : instructions) {
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std::string S;
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raw_string_ostream OS(S);
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II->print(OS);
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OS.flush();
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// Trim the assignment, or start from the begining in the case of a store.
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const size_t i = S.find("=");
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StringInstrMap.push_back({(i == std::string::npos) ? S : S.substr(i), II});
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}
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llvm::sort(StringInstrMap,
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[](const StringInstrPair &a, const StringInstrPair &b) -> bool {
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return (a.first < b.first);
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});
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for (auto &II : StringInstrMap) {
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LLVM_DEBUG({
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dbgs() << "Splicing ";
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II.second->dump();
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dbgs() << " right before: ";
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getPos()->dump();
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});
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Changed = true;
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MBB->splice(getPos(), MBB, II.second);
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}
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return Changed;
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}
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static bool rescheduleCanonically(unsigned &PseudoIdempotentInstCount,
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MachineBasicBlock *MBB) {
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bool Changed = false;
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// Calculates the distance of MI from the begining of its parent BB.
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auto getInstrIdx = [](const MachineInstr &MI) {
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unsigned i = 0;
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for (auto &CurMI : *MI.getParent()) {
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if (&CurMI == &MI)
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return i;
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i++;
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}
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return ~0U;
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};
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// Pre-Populate vector of instructions to reschedule so that we don't
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// clobber the iterator.
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std::vector<MachineInstr *> Instructions;
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for (auto &MI : *MBB) {
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Instructions.push_back(&MI);
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}
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std::map<MachineInstr *, std::vector<MachineInstr *>> MultiUsers;
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std::map<unsigned, MachineInstr *> MultiUserLookup;
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unsigned UseToBringDefCloserToCount = 0;
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std::vector<MachineInstr *> PseudoIdempotentInstructions;
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std::vector<unsigned> PhysRegDefs;
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for (auto *II : Instructions) {
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for (unsigned i = 1; i < II->getNumOperands(); i++) {
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MachineOperand &MO = II->getOperand(i);
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if (!MO.isReg())
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continue;
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if (Register::isVirtualRegister(MO.getReg()))
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continue;
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if (!MO.isDef())
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continue;
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PhysRegDefs.push_back(MO.getReg());
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}
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}
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for (auto *II : Instructions) {
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if (II->getNumOperands() == 0)
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continue;
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if (II->mayLoadOrStore())
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continue;
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MachineOperand &MO = II->getOperand(0);
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if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
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continue;
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if (!MO.isDef())
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continue;
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bool IsPseudoIdempotent = true;
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for (unsigned i = 1; i < II->getNumOperands(); i++) {
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if (II->getOperand(i).isImm()) {
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continue;
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}
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if (II->getOperand(i).isReg()) {
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if (!Register::isVirtualRegister(II->getOperand(i).getReg()))
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if (llvm::find(PhysRegDefs, II->getOperand(i).getReg()) ==
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PhysRegDefs.end()) {
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continue;
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}
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}
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IsPseudoIdempotent = false;
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break;
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}
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if (IsPseudoIdempotent) {
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PseudoIdempotentInstructions.push_back(II);
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continue;
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}
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LLVM_DEBUG(dbgs() << "Operand " << 0 << " of "; II->dump(); MO.dump(););
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MachineInstr *Def = II;
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unsigned Distance = ~0U;
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MachineInstr *UseToBringDefCloserTo = nullptr;
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MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo();
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for (auto &UO : MRI->use_nodbg_operands(MO.getReg())) {
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MachineInstr *UseInst = UO.getParent();
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const unsigned DefLoc = getInstrIdx(*Def);
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const unsigned UseLoc = getInstrIdx(*UseInst);
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const unsigned Delta = (UseLoc - DefLoc);
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if (UseInst->getParent() != Def->getParent())
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continue;
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if (DefLoc >= UseLoc)
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continue;
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if (Delta < Distance) {
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Distance = Delta;
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UseToBringDefCloserTo = UseInst;
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MultiUserLookup[UseToBringDefCloserToCount++] = UseToBringDefCloserTo;
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}
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}
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const auto BBE = MBB->instr_end();
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MachineBasicBlock::iterator DefI = BBE;
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MachineBasicBlock::iterator UseI = BBE;
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for (auto BBI = MBB->instr_begin(); BBI != BBE; ++BBI) {
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if (DefI != BBE && UseI != BBE)
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break;
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if (&*BBI == Def) {
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DefI = BBI;
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continue;
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}
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if (&*BBI == UseToBringDefCloserTo) {
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UseI = BBI;
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continue;
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}
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}
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if (DefI == BBE || UseI == BBE)
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continue;
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LLVM_DEBUG({
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dbgs() << "Splicing ";
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DefI->dump();
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dbgs() << " right before: ";
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UseI->dump();
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});
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MultiUsers[UseToBringDefCloserTo].push_back(Def);
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Changed = true;
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MBB->splice(UseI, MBB, DefI);
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}
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// Sort the defs for users of multiple defs lexographically.
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for (const auto &E : MultiUserLookup) {
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auto UseI =
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std::find_if(MBB->instr_begin(), MBB->instr_end(),
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[&](MachineInstr &MI) -> bool { return &MI == E.second; });
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if (UseI == MBB->instr_end())
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continue;
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LLVM_DEBUG(
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dbgs() << "Rescheduling Multi-Use Instructions Lexographically.";);
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Changed |= rescheduleLexographically(
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MultiUsers[E.second], MBB,
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[&]() -> MachineBasicBlock::iterator { return UseI; });
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}
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PseudoIdempotentInstCount = PseudoIdempotentInstructions.size();
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LLVM_DEBUG(
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dbgs() << "Rescheduling Idempotent Instructions Lexographically.";);
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Changed |= rescheduleLexographically(
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PseudoIdempotentInstructions, MBB,
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[&]() -> MachineBasicBlock::iterator { return MBB->begin(); });
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return Changed;
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}
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static bool propagateLocalCopies(MachineBasicBlock *MBB) {
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bool Changed = false;
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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std::vector<MachineInstr *> Copies;
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for (MachineInstr &MI : MBB->instrs()) {
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if (MI.isCopy())
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Copies.push_back(&MI);
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}
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for (MachineInstr *MI : Copies) {
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if (!MI->getOperand(0).isReg())
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continue;
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if (!MI->getOperand(1).isReg())
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continue;
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const Register Dst = MI->getOperand(0).getReg();
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const Register Src = MI->getOperand(1).getReg();
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if (!Register::isVirtualRegister(Dst))
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continue;
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if (!Register::isVirtualRegister(Src))
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continue;
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// Not folding COPY instructions if regbankselect has not set the RCs.
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// Why are we only considering Register Classes? Because the verifier
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// sometimes gets upset if the register classes don't match even if the
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// types do. A future patch might add COPY folding for matching types in
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// pre-registerbankselect code.
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if (!MRI.getRegClassOrNull(Dst))
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continue;
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if (MRI.getRegClass(Dst) != MRI.getRegClass(Src))
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continue;
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std::vector<MachineOperand *> Uses;
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for (auto UI = MRI.use_begin(Dst); UI != MRI.use_end(); ++UI)
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Uses.push_back(&*UI);
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for (auto *MO : Uses)
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MO->setReg(Src);
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Changed = true;
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MI->eraseFromParent();
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}
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return Changed;
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}
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static bool doDefKillClear(MachineBasicBlock *MBB) {
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bool Changed = false;
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for (auto &MI : *MBB) {
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for (auto &MO : MI.operands()) {
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if (!MO.isReg())
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continue;
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if (!MO.isDef() && MO.isKill()) {
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Changed = true;
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MO.setIsKill(false);
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}
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if (MO.isDef() && MO.isDead()) {
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Changed = true;
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MO.setIsDead(false);
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}
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}
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}
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return Changed;
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}
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static bool runOnBasicBlock(MachineBasicBlock *MBB,
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unsigned BasicBlockNum, VRegRenamer &Renamer) {
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LLVM_DEBUG({
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dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << " \n\n";
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dbgs() << "\n\n================================================\n\n";
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});
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bool Changed = false;
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LLVM_DEBUG(dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << "\n\n";);
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LLVM_DEBUG(dbgs() << "MBB Before Canonical Copy Propagation:\n";
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MBB->dump(););
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Changed |= propagateLocalCopies(MBB);
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LLVM_DEBUG(dbgs() << "MBB After Canonical Copy Propagation:\n"; MBB->dump(););
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LLVM_DEBUG(dbgs() << "MBB Before Scheduling:\n"; MBB->dump(););
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unsigned IdempotentInstCount = 0;
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Changed |= rescheduleCanonically(IdempotentInstCount, MBB);
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LLVM_DEBUG(dbgs() << "MBB After Scheduling:\n"; MBB->dump(););
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Changed |= Renamer.renameVRegs(MBB, BasicBlockNum);
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// TODO: Consider dropping this. Dropping kill defs is probably not
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// semantically sound.
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Changed |= doDefKillClear(MBB);
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LLVM_DEBUG(dbgs() << "Updated MachineBasicBlock:\n"; MBB->dump();
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dbgs() << "\n";);
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LLVM_DEBUG(
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dbgs() << "\n\n================================================\n\n");
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return Changed;
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}
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bool MIRCanonicalizer::runOnMachineFunction(MachineFunction &MF) {
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static unsigned functionNum = 0;
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if (CanonicalizeFunctionNumber != ~0U) {
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if (CanonicalizeFunctionNumber != functionNum++)
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return false;
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LLVM_DEBUG(dbgs() << "\n Canonicalizing Function " << MF.getName()
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<< "\n";);
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}
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// we need a valid vreg to create a vreg type for skipping all those
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// stray vreg numbers so reach alignment/canonical vreg values.
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std::vector<MachineBasicBlock *> RPOList = GetRPOList(MF);
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LLVM_DEBUG(
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dbgs() << "\n\n NEW MACHINE FUNCTION: " << MF.getName() << " \n\n";
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dbgs() << "\n\n================================================\n\n";
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dbgs() << "Total Basic Blocks: " << RPOList.size() << "\n";
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for (auto MBB
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: RPOList) { dbgs() << MBB->getName() << "\n"; } dbgs()
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<< "\n\n================================================\n\n";);
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unsigned BBNum = 0;
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bool Changed = false;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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VRegRenamer Renamer(MRI);
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for (auto MBB : RPOList)
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Changed |= runOnBasicBlock(MBB, BBNum++, Renamer);
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return Changed;
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}
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