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cf654d4aae
Reduce to forward declaration, add the Register.h include that we still needed, move CCState::ensureMaxAlignment into CallingConvLower.cpp as it was the only function that needed the full definition of MachineFunction. Fix a few implicit dependencies further down.
294 lines
11 KiB
C++
294 lines
11 KiB
C++
//===-- CallingConvLower.cpp - Calling Conventions ------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the CCState class, used for lowering and implementing
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// calling conventions.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/SaveAndRestore.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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using namespace llvm;
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CCState::CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &mf,
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SmallVectorImpl<CCValAssign> &locs, LLVMContext &C)
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: CallingConv(CC), IsVarArg(isVarArg), MF(mf),
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TRI(*MF.getSubtarget().getRegisterInfo()), Locs(locs), Context(C) {
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// No stack is used.
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StackOffset = 0;
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clearByValRegsInfo();
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UsedRegs.resize((TRI.getNumRegs()+31)/32);
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}
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/// Allocate space on the stack large enough to pass an argument by value.
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/// The size and alignment information of the argument is encoded in
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/// its parameter attribute.
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void CCState::HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo, int MinSize,
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Align MinAlign, ISD::ArgFlagsTy ArgFlags) {
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Align Alignment = ArgFlags.getNonZeroByValAlign();
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unsigned Size = ArgFlags.getByValSize();
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if (MinSize > (int)Size)
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Size = MinSize;
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if (MinAlign > Alignment)
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Alignment = MinAlign;
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ensureMaxAlignment(Alignment);
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MF.getSubtarget().getTargetLowering()->HandleByVal(this, Size, Alignment);
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Size = unsigned(alignTo(Size, MinAlign));
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unsigned Offset = AllocateStack(Size, Alignment);
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addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
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}
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/// Mark a register and all of its aliases as allocated.
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void CCState::MarkAllocated(MCPhysReg Reg) {
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for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
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UsedRegs[*AI / 32] |= 1 << (*AI & 31);
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}
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bool CCState::IsShadowAllocatedReg(MCRegister Reg) const {
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if (!isAllocated(Reg))
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return false;
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for (auto const &ValAssign : Locs) {
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if (ValAssign.isRegLoc()) {
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for (MCRegAliasIterator AI(ValAssign.getLocReg(), &TRI, true);
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AI.isValid(); ++AI) {
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if (*AI == Reg)
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return false;
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}
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}
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}
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return true;
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}
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/// Analyze an array of argument values,
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/// incorporating info about the formals into this state.
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void
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CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
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CCAssignFn Fn) {
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unsigned NumArgs = Ins.size();
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for (unsigned i = 0; i != NumArgs; ++i) {
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MVT ArgVT = Ins[i].VT;
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ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
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if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this))
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report_fatal_error("unable to allocate function argument #" + Twine(i));
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}
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}
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/// Analyze the return values of a function, returning true if the return can
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/// be performed without sret-demotion and false otherwise.
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bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
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CCAssignFn Fn) {
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// Determine which register each value should be copied into.
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for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
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MVT VT = Outs[i].VT;
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ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
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if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
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return false;
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}
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return true;
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}
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/// Analyze the returned values of a return,
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/// incorporating info about the result values into this state.
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void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
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CCAssignFn Fn) {
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// Determine which register each value should be copied into.
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for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
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MVT VT = Outs[i].VT;
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ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
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if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
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report_fatal_error("unable to allocate function return #" + Twine(i));
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}
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}
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/// Analyze the outgoing arguments to a call,
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/// incorporating info about the passed values into this state.
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void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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CCAssignFn Fn) {
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unsigned NumOps = Outs.size();
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for (unsigned i = 0; i != NumOps; ++i) {
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MVT ArgVT = Outs[i].VT;
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ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
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if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
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#ifndef NDEBUG
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dbgs() << "Call operand #" << i << " has unhandled type "
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<< EVT(ArgVT).getEVTString() << '\n';
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#endif
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llvm_unreachable(nullptr);
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}
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}
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}
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/// Same as above except it takes vectors of types and argument flags.
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void CCState::AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
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SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
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CCAssignFn Fn) {
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unsigned NumOps = ArgVTs.size();
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for (unsigned i = 0; i != NumOps; ++i) {
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MVT ArgVT = ArgVTs[i];
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ISD::ArgFlagsTy ArgFlags = Flags[i];
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if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
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#ifndef NDEBUG
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dbgs() << "Call operand #" << i << " has unhandled type "
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<< EVT(ArgVT).getEVTString() << '\n';
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#endif
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llvm_unreachable(nullptr);
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}
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}
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}
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/// Analyze the return values of a call, incorporating info about the passed
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/// values into this state.
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void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
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CCAssignFn Fn) {
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for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
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MVT VT = Ins[i].VT;
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ISD::ArgFlagsTy Flags = Ins[i].Flags;
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if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) {
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#ifndef NDEBUG
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dbgs() << "Call result #" << i << " has unhandled type "
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<< EVT(VT).getEVTString() << '\n';
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#endif
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llvm_unreachable(nullptr);
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}
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}
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}
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/// Same as above except it's specialized for calls that produce a single value.
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void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) {
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if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) {
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#ifndef NDEBUG
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dbgs() << "Call result has unhandled type "
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<< EVT(VT).getEVTString() << '\n';
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#endif
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llvm_unreachable(nullptr);
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}
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}
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void CCState::ensureMaxAlignment(Align Alignment) {
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if (!AnalyzingMustTailForwardedRegs)
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MF.getFrameInfo().ensureMaxAlignment(Alignment);
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}
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static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) {
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if (VT.isVector())
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return true; // Assume -msse-regparm might be in effect.
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if (!VT.isInteger())
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return false;
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if (CC == CallingConv::X86_VectorCall || CC == CallingConv::X86_FastCall)
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return true;
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return false;
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}
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void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs,
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MVT VT, CCAssignFn Fn) {
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unsigned SavedStackOffset = StackOffset;
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Align SavedMaxStackArgAlign = MaxStackArgAlign;
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unsigned NumLocs = Locs.size();
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// Set the 'inreg' flag if it is used for this calling convention.
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ISD::ArgFlagsTy Flags;
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if (isValueTypeInRegForCC(CallingConv, VT))
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Flags.setInReg();
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// Allocate something of this value type repeatedly until we get assigned a
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// location in memory.
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bool HaveRegParm = true;
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while (HaveRegParm) {
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if (Fn(0, VT, VT, CCValAssign::Full, Flags, *this)) {
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#ifndef NDEBUG
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dbgs() << "Call has unhandled type " << EVT(VT).getEVTString()
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<< " while computing remaining regparms\n";
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#endif
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llvm_unreachable(nullptr);
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}
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HaveRegParm = Locs.back().isRegLoc();
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}
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// Copy all the registers from the value locations we added.
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assert(NumLocs < Locs.size() && "CC assignment failed to add location");
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for (unsigned I = NumLocs, E = Locs.size(); I != E; ++I)
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if (Locs[I].isRegLoc())
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Regs.push_back(MCPhysReg(Locs[I].getLocReg()));
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// Clear the assigned values and stack memory. We leave the registers marked
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// as allocated so that future queries don't return the same registers, i.e.
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// when i64 and f64 are both passed in GPRs.
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StackOffset = SavedStackOffset;
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MaxStackArgAlign = SavedMaxStackArgAlign;
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Locs.resize(NumLocs);
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}
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void CCState::analyzeMustTailForwardedRegisters(
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SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
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CCAssignFn Fn) {
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// Oftentimes calling conventions will not user register parameters for
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// variadic functions, so we need to assume we're not variadic so that we get
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// all the registers that might be used in a non-variadic call.
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SaveAndRestore<bool> SavedVarArg(IsVarArg, false);
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SaveAndRestore<bool> SavedMustTail(AnalyzingMustTailForwardedRegs, true);
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for (MVT RegVT : RegParmTypes) {
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SmallVector<MCPhysReg, 8> RemainingRegs;
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getRemainingRegParmsForType(RemainingRegs, RegVT, Fn);
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const TargetLowering *TL = MF.getSubtarget().getTargetLowering();
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const TargetRegisterClass *RC = TL->getRegClassFor(RegVT);
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for (MCPhysReg PReg : RemainingRegs) {
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unsigned VReg = MF.addLiveIn(PReg, RC);
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Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT));
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}
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}
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}
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bool CCState::resultsCompatible(CallingConv::ID CalleeCC,
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CallingConv::ID CallerCC, MachineFunction &MF,
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LLVMContext &C,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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CCAssignFn CalleeFn, CCAssignFn CallerFn) {
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if (CalleeCC == CallerCC)
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return true;
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SmallVector<CCValAssign, 4> RVLocs1;
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CCState CCInfo1(CalleeCC, false, MF, RVLocs1, C);
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CCInfo1.AnalyzeCallResult(Ins, CalleeFn);
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SmallVector<CCValAssign, 4> RVLocs2;
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CCState CCInfo2(CallerCC, false, MF, RVLocs2, C);
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CCInfo2.AnalyzeCallResult(Ins, CallerFn);
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if (RVLocs1.size() != RVLocs2.size())
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return false;
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for (unsigned I = 0, E = RVLocs1.size(); I != E; ++I) {
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const CCValAssign &Loc1 = RVLocs1[I];
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const CCValAssign &Loc2 = RVLocs2[I];
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if ( // Must both be in registers, or both in memory
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Loc1.isRegLoc() != Loc2.isRegLoc() ||
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// Must fill the same part of their locations
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Loc1.getLocInfo() != Loc2.getLocInfo() ||
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// Memory offset/register number must be the same
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Loc1.getExtraInfo() != Loc2.getExtraInfo())
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return false;
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}
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return true;
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}
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