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llvm-mirror/test/CodeGen/AMDGPU/GlobalISel
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Tim Northover aebb01e004 GlobalISel: implement low-level type with just size & vector lanes. 
This should be all the low-level instruction selection needs to determine how
to implement an operation, with the remaining context taken from the opcode
(e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math).

llvm-svn: 276158
2016-07-20 19:09:30 +00:00
..
amdgpu-irtranslator.ll