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AArch64
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[MC] [Win64EH] Try to generate packed unwind info where possible
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2020-09-23 09:03:01 +03:00 |
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AMDGPU
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[AMDGPU][MC][GFX1030] Disabled v_mac_f32
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2020-10-08 14:00:52 +03:00 |
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ARM
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llvm-dwarfdump: Dump address forms in their encoded length rather than always in 64 bits
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2020-10-04 15:48:57 -07:00 |
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AsmParser
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Introduce and use a new section type for the bb_addr_map section.
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2020-10-08 11:13:19 -07:00 |
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AVR
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[AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex
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2020-07-12 08:14:52 -07:00 |
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BPF
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COFF
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[test][MC] Use %python in llvm/test/MC/COFF/bigobj.py
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2020-10-07 14:03:28 -04:00 |
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Disassembler
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[PowerPC] Add outer product instructions for MMA
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2020-09-30 18:06:49 -05:00 |
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ELF
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Show register names in DWARF unwind info.
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2020-10-05 15:34:33 -07:00 |
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Hexagon
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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Lanai
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MachO
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llvm-dwarfdump: Dump address forms in their encoded length rather than always in 64 bits
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2020-10-04 15:48:57 -07:00 |
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Mips
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Show register names in DWARF unwind info.
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2020-10-05 15:34:33 -07:00 |
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MSP430
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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PowerPC
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[PowerPC] Add outer product instructions for MMA
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2020-09-30 18:06:49 -05:00 |
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RISCV
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[RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.
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2020-10-02 17:20:34 +08:00 |
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Sparc
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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SystemZ
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[SystemZAsmParser] Treat VR128 separately in ParseDirectiveInsn().
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2020-10-06 14:42:40 +02:00 |
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VE
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WebAssembly
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[WebAssembly] Prototype i16x8.q15mulr_sat_s
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2020-10-09 21:17:53 +00:00 |
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X86
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[X86] .code16: temporarily set Mode32Bit when matching an instruction with the data32 prefix
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2020-10-06 08:32:03 -07:00 |
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