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da9360e77e
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). <rant>DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen.</rant> llvm-svn: 62990
8 lines
188 B
LLVM
8 lines
188 B
LLVM
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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define i1 @fcmp_eq_setcc_f64(double %arg1, double %arg2) nounwind {
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entry:
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%A = fcmp oeq double %arg1, %arg2
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ret i1 %A
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}
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