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120 lines
4.6 KiB
C++
120 lines
4.6 KiB
C++
//===---- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG class ---==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This declares the Emit routines for the SelectionDAG class, which creates
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// MachineInstrs based on the decisions of the SelectionDAG instruction
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// selection.
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//
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//===----------------------------------------------------------------------===//
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#ifndef INSTREMITTER_H
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#define INSTREMITTER_H
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/ADT/DenseMap.h"
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namespace llvm {
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class TargetInstrDesc;
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class InstrEmitter {
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MachineFunction *MF;
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MachineRegisterInfo *MRI;
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const TargetLowering *TLI;
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MachineBasicBlock *MBB;
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MachineBasicBlock::iterator InsertPos;
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/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
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/// implicit physical register output.
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void EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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bool IsClone, bool IsCloned,
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unsigned SrcReg,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// getDstOfCopyToRegUse - If the only use of the specified result number of
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/// node is a CopyToReg, return its destination register. Return 0 otherwise.
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unsigned getDstOfOnlyCopyToRegUse(SDNode *Node,
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unsigned ResNo) const;
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void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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const TargetInstrDesc &II,
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bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// getVR - Return the virtual register corresponding to the specified result
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/// of the specified node.
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unsigned getVR(SDValue Op,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// AddRegisterOperand - Add the specified register as an operand to the
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/// specified machine instr. Insert register copies if the register is
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/// not in the required register class.
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void AddRegisterOperand(MachineInstr *MI, SDValue Op,
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unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// AddOperand - Add the specified operand to the specified machine instr. II
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/// specifies the instruction information for the node, and IIOpNum is the
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/// operand number (in the II) that we are adding. IIOpNum and II are used for
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/// assertions only.
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void AddOperand(MachineInstr *MI, SDValue Op,
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unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// EmitSubregNode - Generate machine code for subreg nodes.
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///
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void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap);
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/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
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/// COPY_TO_REGCLASS is just a normal copy, except that the destination
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/// register is constrained to be in a particular register class.
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///
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void EmitCopyToRegClassNode(SDNode *Node,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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public:
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional flag operands
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/// (which do not go into the machine instrs.)
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static unsigned CountResults(SDNode *Node);
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/// CountOperands - The inputs to target nodes have any actual inputs first,
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/// followed by an optional chain operand, then flag operands. Compute
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/// the number of actual operands that will go into the resulting
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/// MachineInstr.
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static unsigned CountOperands(SDNode *Node);
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/// EmitNode - Generate machine code for a node and needed dependencies.
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///
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void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
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/// getBlock - Return the current basic block.
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MachineBasicBlock *getBlock() { return MBB; }
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/// getInsertPos - Return the current insertion position.
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MachineBasicBlock::iterator getInsertPos() { return InsertPos; }
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/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
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/// at the given position in the given block.
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InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos);
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};
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}
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#endif
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