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139c1152ca
On 64-bit targets the generic legalize will use an i64 load and a scalar_to_vector for us. But on 32-bit targets i64 isn't legal and the generic legalizer will end up emitting two 32-bit loads. We have DAG combines that try to put those two loads back together with pretty good success. This patch instead uses f64 to avoid the splitting entirely. I've made it do the same for 64-bit mode for consistency and to keep the load in the fp domain. There are a few things in here that look like regressions in 32-bit mode, but I believe they bring us closer to the 64-bit mode codegen. And that the 64-bit mode code could be better. I think those issues should be looked at separately. Differential Revision: https://reviews.llvm.org/D52528 llvm-svn: 344291
40 lines
1.3 KiB
LLVM
40 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86-SSE
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
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define i1 @foo(i64 %a) {
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; X86-LABEL: foo:
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; X86: # %bb.0:
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; X86-NEXT: flds {{[0-9]+}}(%esp)
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; X86-NEXT: flds {{[0-9]+}}(%esp)
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; X86-NEXT: fucompp
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; X86-NEXT: fnstsw %ax
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; X86-NEXT: # kill: def $ah killed $ah killed $ax
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; X86-NEXT: sahf
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; X86-NEXT: setp %al
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; X86-NEXT: retl
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;
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; X86-SSE-LABEL: foo:
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; X86-SSE: # %bb.0:
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; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-SSE-NEXT: movaps %xmm0, %xmm1
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; X86-SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[2,3]
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; X86-SSE-NEXT: ucomiss %xmm1, %xmm0
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; X86-SSE-NEXT: setp %al
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; X86-SSE-NEXT: retl
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;
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; X64-LABEL: foo:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %xmm0
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
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; X64-NEXT: ucomiss %xmm1, %xmm0
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; X64-NEXT: setp %al
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; X64-NEXT: retq
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%t = bitcast i64 %a to <2 x float>
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%r = extractelement <2 x float> %t, i32 0
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%s = extractelement <2 x float> %t, i32 1
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%b = fcmp uno float %r, %s
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ret i1 %b
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}
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