Craig Topper 707737eef4 [DAGCombiner][AMDGPU][Mips] Fold bitcast with volatile loads if the resulting load is legal for the target. ... Summary: I'm not sure if this patch is correct or if it needs more qualifying somehow. Bitcast shouldn't change the size of the load so it should be ok? We already do something similar for stores. We'll change the type of a volatile store if the resulting store is Legal or Custom. I'm not sure we should be allowing Custom there... I was playing around with converting X86 atomic loads/stores(except seq_cst) into regular volatile loads and stores during lowering. This would allow some special RMW isel patterns in X86InstrCompiler.td to be removed. But there's some floating point patterns in there that didn't work because we don't fold (f64 (bitconvert (i64 volatile load))) or (f32 (bitconvert (i32 volatile load))). Reviewers: efriedma, atanasyan, arsenm Reviewed By: efriedma Subscribers: jvesely, arsenm, sdardis, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, arichardson, jrtc27, atanasyan, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D50491 llvm-svn: 340797		2018-08-28 03:47:20 +00:00
..
CMakeLists.txt
DAGCombiner.cpp	[DAGCombiner][AMDGPU][Mips] Fold bitcast with volatile loads if the resulting load is legal for the target.	2018-08-28 03:47:20 +00:00
FastISel.cpp	[IR] Replace isa<TerminatorInst> with isTerminator().	2018-08-26 09:51:22 +00:00
FunctionLoweringInfo.cpp	DAG: Add calling convention argument to calling convention funcs	2018-07-28 13:25:19 +00:00
InstrEmitter.cpp	[MI] Change the array of MachineMemOperand pointers to be	2018-08-16 21:30:05 +00:00
InstrEmitter.h
LegalizeDAG.cpp	[ARM] Lower llvm.ctlz.i32 to a libcall when clz is not available.	2018-08-22 21:47:14 +00:00
LegalizeFloatTypes.cpp	DAG: Try to custom lower when promoting float operands	2018-08-15 20:34:54 +00:00
LegalizeIntegerTypes.cpp	[SelectionDAG][X86] Reorder the operands the MaskedStoreSDNode to put the value first.	2018-08-25 17:48:17 +00:00
LegalizeTypes.cpp
LegalizeTypes.h	[FPEnv] Scalarize StrictFP vector operations	2018-08-14 22:13:11 +00:00
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp	[FPEnv] Support constrained FREM intrinsic	2018-08-20 19:28:56 +00:00
LegalizeVectorTypes.cpp	[SelectionDAG][X86] Reorder the operands the MaskedStoreSDNode to put the value first.	2018-08-25 17:48:17 +00:00
LLVMBuild.txt
ResourcePriorityQueue.cpp
ScheduleDAGFast.cpp
ScheduleDAGRRList.cpp	[ScheduleDAG] Fix unfolding of SUnits to already existent nodes.	2018-07-18 18:01:03 +00:00
ScheduleDAGSDNodes.cpp	[SDAG] Remove the reliance on MI's allocation strategy for	2018-08-14 23:30:32 +00:00
ScheduleDAGSDNodes.h	[CodeGen] Fix inconsistent declaration parameter name	2018-07-16 18:51:40 +00:00
ScheduleDAGVLIW.cpp
SDNodeDbgValue.h	[DebugInfo] LowerDbgDeclare: Add derefs when handling CallInst users	2018-07-26 20:56:53 +00:00
SelectionDAG.cpp	[SelectionDAG][X86] Reorder the operands the MaskedStoreSDNode to put the value first.	2018-08-25 17:48:17 +00:00
SelectionDAGAddressAnalysis.cpp
SelectionDAGBuilder.cpp	[IR] Replace isa<TerminatorInst> with isTerminator().	2018-08-26 09:51:22 +00:00
SelectionDAGBuilder.h	DAG: Add calling convention argument to calling convention funcs	2018-07-28 13:25:19 +00:00
SelectionDAGDumper.cpp
SelectionDAGISel.cpp	[IR] Replace isa<TerminatorInst> with isTerminator().	2018-08-26 09:51:22 +00:00
SelectionDAGPrinter.cpp
SelectionDAGTargetInfo.cpp
StatepointLowering.cpp	Remove trailing space	2018-07-30 19:41:25 +00:00
StatepointLowering.h
TargetLowering.cpp	[TargetLowering] Add BuildSDiv support for division by one or negone.	2018-08-21 10:20:36 +00:00