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9d874b8ed0
Summary:
This allows Mesa to pass initial SPI_PS_INPUT_ADDR to LLVM.
The register assigns VGPR locations to PS inputs, while the ENA register
determines whether or not they are loaded.
Mesa needs to set some inputs as not-movable, so that a pixel shader prolog
binary appended at the beginning can assume where some inputs are.
v2: Make PSInputAddr private, because there is never enough silly getters
and setters for people to read.
Reviewers: tstellarAMD, arsenm
Subscribers: arsenm
Differential Revision: http://reviews.llvm.org/D16030
llvm-svn: 257591
63 lines
1.7 KiB
C++
63 lines
1.7 KiB
C++
//===-- AMDGPUBaseInfo.h - Top level definitions for AMDGPU -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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#include "AMDKernelCodeT.h"
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namespace llvm {
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class FeatureBitset;
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class Function;
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class GlobalValue;
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class MCContext;
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class MCSection;
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class MCSubtargetInfo;
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namespace AMDGPU {
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struct IsaVersion {
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unsigned Major;
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unsigned Minor;
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unsigned Stepping;
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};
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IsaVersion getIsaVersion(const FeatureBitset &Features);
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void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
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const FeatureBitset &Features);
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MCSection *getHSATextSection(MCContext &Ctx);
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MCSection *getHSADataGlobalAgentSection(MCContext &Ctx);
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MCSection *getHSADataGlobalProgramSection(MCContext &Ctx);
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MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx);
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bool isGroupSegment(const GlobalValue *GV);
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bool isGlobalSegment(const GlobalValue *GV);
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bool isReadOnlySegment(const GlobalValue *GV);
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unsigned getShaderType(const Function &F);
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unsigned getInitialPSInputAddr(const Function &F);
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bool isSI(const MCSubtargetInfo &STI);
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bool isCI(const MCSubtargetInfo &STI);
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bool isVI(const MCSubtargetInfo &STI);
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/// If \p Reg is a pseudo reg, return the correct hardware register given
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/// \p STI otherwise return \p Reg.
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unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
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} // end namespace AMDGPU
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} // end namespace llvm
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#endif
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