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585b4225c3
llvm-svn: 151996
133 lines
4.3 KiB
C++
133 lines
4.3 KiB
C++
//===-- RegisterClassInfo.h - Dynamic Register Class Info -*- C++ -*-------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RegisterClassInfo class which provides dynamic
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// information about target register classes. Callee saved and reserved
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// registers depends on calling conventions and other dynamic information, so
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// some things cannot be determined statically.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
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#define LLVM_CODEGEN_REGISTERCLASSINFO_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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namespace llvm {
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class RegisterClassInfo {
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struct RCInfo {
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unsigned Tag;
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unsigned NumRegs;
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bool ProperSubClass;
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OwningArrayPtr<unsigned> Order;
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RCInfo() : Tag(0), NumRegs(0), ProperSubClass(false) {}
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operator ArrayRef<unsigned>() const {
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return makeArrayRef(Order.get(), NumRegs);
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}
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};
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// Brief cached information for each register class.
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OwningArrayPtr<RCInfo> RegClass;
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// Tag changes whenever cached information needs to be recomputed. An RCInfo
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// entry is valid when its tag matches.
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unsigned Tag;
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const MachineFunction *MF;
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const TargetRegisterInfo *TRI;
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// Callee saved registers of last MF. Assumed to be valid until the next
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// runOnFunction() call.
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const uint16_t *CalleeSaved;
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// Map register number to CalleeSaved index + 1;
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SmallVector<uint8_t, 4> CSRNum;
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// Reserved registers in the current MF.
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BitVector Reserved;
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// Compute all information about RC.
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void compute(const TargetRegisterClass *RC) const;
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// Return an up-to-date RCInfo for RC.
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const RCInfo &get(const TargetRegisterClass *RC) const {
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const RCInfo &RCI = RegClass[RC->getID()];
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if (Tag != RCI.Tag)
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compute(RC);
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return RCI;
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}
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public:
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RegisterClassInfo();
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/// runOnFunction - Prepare to answer questions about MF. This must be called
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/// before any other methods are used.
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void runOnMachineFunction(const MachineFunction &MF);
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/// getNumAllocatableRegs - Returns the number of actually allocatable
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/// registers in RC in the current function.
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unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
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return get(RC).NumRegs;
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}
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/// getOrder - Returns the preferred allocation order for RC. The order
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/// contains no reserved registers, and registers that alias callee saved
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/// registers come last.
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ArrayRef<unsigned> getOrder(const TargetRegisterClass *RC) const {
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return get(RC);
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}
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/// isProperSubClass - Returns true if RC has a legal super-class with more
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/// allocatable registers.
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///
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/// Register classes like GR32_NOSP are not proper sub-classes because %esp
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/// is not allocatable. Similarly, tGPR is not a proper sub-class in Thumb
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/// mode because the GPR super-class is not legal.
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bool isProperSubClass(const TargetRegisterClass *RC) const {
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return get(RC).ProperSubClass;
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}
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/// getLastCalleeSavedAlias - Returns the last callee saved register that
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/// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
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unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
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assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
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if (unsigned N = CSRNum[PhysReg])
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return CalleeSaved[N-1];
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return 0;
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}
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/// isReserved - Returns true when PhysReg is a reserved register.
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///
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/// Reserved registers may belong to an allocatable register class, but the
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/// target has explicitly requested that they are not used.
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///
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bool isReserved(unsigned PhysReg) const {
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return Reserved.test(PhysReg);
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}
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/// isAllocatable - Returns true when PhysReg belongs to an allocatable
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/// register class and it hasn't been reserved.
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///
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/// Allocatable registers may show up in the allocation order of some virtual
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/// register, so a register allocator needs to track its liveness and
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/// availability.
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bool isAllocatable(unsigned PhysReg) const {
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return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
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}
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};
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} // end namespace llvm
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#endif
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