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AArch64
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[CodeGen] Print register names in lowercase in both MIR and debug output
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2017-11-28 17:15:09 +00:00 |
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AMDGPU
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AMDGPU: Add num spilled s/vgprs to metadata
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2017-11-28 17:51:08 +00:00 |
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ARC
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ARM
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[CodeGen] Print register names in lowercase in both MIR and debug output
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2017-11-28 17:15:09 +00:00 |
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AVR
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[AVR] Use the short form of 'clr <reg>'
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2017-11-24 15:36:43 +00:00 |
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BPF
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[CodeGen] Print register names in lowercase in both MIR and debug output
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2017-11-28 17:15:09 +00:00 |
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Generic
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[CodeGen] Peel off the dominant case in switch statement in lowering
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2017-11-14 21:44:09 +00:00 |
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Hexagon
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[Hexagon] Make sure to zero-extend bytes before building a vector
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2017-11-28 19:13:17 +00:00 |
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Inputs
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Lanai
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Mips
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[CodeGen] Print register names in lowercase in both MIR and debug output
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2017-11-28 17:15:09 +00:00 |
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MIR
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[mir] Print/Parse both MOLoad and MOStore when they occur together.
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2017-11-28 18:57:02 +00:00 |
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MSP430
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Nios2
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NVPTX
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PowerPC
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[CodeGen] Print register names in lowercase in both MIR and debug output
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2017-11-28 17:15:09 +00:00 |
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RISCV
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[RISCV] Use register X0 (ZERO) for constant 0
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2017-11-21 08:23:08 +00:00 |
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SPARC
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[Sparc] efficient pattern for UINT_TO_FP conversion
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2017-11-20 22:33:58 +00:00 |
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SystemZ
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[CodeGen] Print register names in lowercase in both MIR and debug output
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2017-11-28 17:15:09 +00:00 |
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Thumb
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[ARM] Fix an off-by-one error when restoring LR for 16-bit Thumb
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2017-11-27 10:13:14 +00:00 |
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Thumb2
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[arm] Fix Unnecessary reloads from GOT.
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2017-11-13 20:45:38 +00:00 |
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WebAssembly
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[WebAssembly] Support bitcasted function addresses with varargs.
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2017-11-28 17:15:03 +00:00 |
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WinEH
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X86
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[CodeGen] Print register names in lowercase in both MIR and debug output
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2017-11-28 17:15:09 +00:00 |
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XCore
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