Alex Bradbury 5a992b5fc4 [TableGen] Give the option of tolerating duplicate register names ... A number of architectures re-use the same register names (e.g. for both 32-bit FPRs and 64-bit FPRs). They are currently unable to use the tablegen'erated MatchRegisterName and MatchRegisterAltName, as tablegen (when built with asserts enabled) will fail. When the AllowDuplicateRegisterNames in AsmParser is set, duplicated register names will be tolerated. A backend can then coerce registers to the desired register class by (for instance) implementing validateTargetOperandClass. At least the in-tree Sparc backend could benefit from this, as does RISC-V (single and double precision floating point registers). Differential Revision: https://reviews.llvm.org/D39845 llvm-svn: 320018		2017-12-07 09:51:55 +00:00
..
CMakeLists.txt
Error.cpp	[globalisel][regbank] Warn about MIR ambiguities when register bank/class names clash.	2017-11-01 22:13:05 +00:00
LLVMBuild.txt
Main.cpp	[Support] Rename tool_output_file to ToolOutputFile, NFC	2017-09-23 01:03:17 +00:00
Record.cpp	Reverting r315590; it did not include changes for llvm-tblgen, which is causing link errors for several people.	2017-10-15 14:32:27 +00:00
SetTheory.cpp	[BinaryFormat, Option, TableGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).	2017-06-16 00:43:26 +00:00
StringMatcher.cpp	[TableGen] Give the option of tolerating duplicate register names	2017-12-07 09:51:55 +00:00
TableGenBackend.cpp
TGLexer.cpp	TableGen: Add operator !or	2016-11-15 06:49:28 +00:00
TGLexer.h	TableGen: Add operator !or	2016-11-15 06:49:28 +00:00
TGParser.cpp	Reverting r315590; it did not include changes for llvm-tblgen, which is causing link errors for several people.	2017-10-15 14:32:27 +00:00
TGParser.h	[TableGen] Remove RecordVal constructor that takes a StringRef and Record::setName(StringRef). Leave just the versions that take an Init.	2017-06-01 06:56:16 +00:00