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486da6004f
To save a 'add sp,#val' instruction by adding registers to the final pop instruction, the first register transferred by this pop instruction need to be found. If the function to be optimized has a non-void return value, the operand list contains r0 (implicit) which prevents the optimization to take place. Therefore implicit register references should be skipped in the search loop, because this registers are never popped from the stack. Patch by Rainer Herbertz (rOptimizer)! Differential revision: https://reviews.llvm.org/D66730 llvm-svn: 370728
253 lines
7.3 KiB
LLVM
253 lines
7.3 KiB
LLVM
; Disable shrink-wrapping on the first test otherwise we wouldn't
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; exerce the path for PR18136.
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; RUN: llc -mtriple=thumbv7-apple-none-macho < %s -enable-shrink-wrap=false -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-FNSTART,CHECK
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; RUN: llc -mtriple=thumbv6m-apple-none-macho -frame-pointer=all < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-FNSTART,CHECK-T1
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; RUN: llc -mtriple=thumbv6m-apple-none-macho < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-FNSTART,CHECK-T1-NOFP
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; RUN: llc -mtriple=thumbv7-apple-darwin-ios -frame-pointer=all < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-FNSTART,CHECK-IOS
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; RUN: llc -mtriple=thumbv7--linux-gnueabi -frame-pointer=all < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK-FNSTART,CHECK-LINUX
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declare void @bar(i8*)
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%bigVec = type [2 x double]
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@var = global %bigVec zeroinitializer
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define void @check_simple() minsize {
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; CHECK-FNSTART-LABEL: check_simple:
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; CHECK: push {r3, r4, r5, r6, r7, lr}
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; CHECK-NOT: sub sp, sp,
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; ...
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; CHECK-NOT: add sp, sp,
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; CHECK: pop {r0, r1, r2, r3, r7, pc}
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; CHECK-T1: push {r3, r4, r5, r6, r7, lr}
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; CHECK-T1: add r7, sp, #16
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; CHECK-T1-NOT: sub sp, sp,
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; ...
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; CHECK-T1-NOT: add sp, sp,
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; CHECK-T1: pop {r0, r1, r2, r3, r7, pc}
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; iOS always has a frame pointer and messing with the push affects
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; how it's set in the prologue. Make sure we get that right.
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; CHECK-IOS: push {r3, r4, r5, r6, r7, lr}
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; CHECK-NOT: sub sp,
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; CHECK-IOS: add r7, sp, #16
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; CHECK-NOT: sub sp,
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; ...
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; CHECK-NOT: add sp,
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; CHEC: pop {r3, r4, r5, r6, r7, pc}
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%var = alloca i8, i32 16
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call void @bar(i8* %var)
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ret void
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}
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define i32 @check_simple_ret() minsize {
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; CHECK-FNSTART-LABEL: check_simple_ret:
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; CHECK: push {r5, r6, r7, lr}
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; CHECK-NOT: sub sp,
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; ...
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; CHECK-NOT: add sp,
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; CHECK: pop {r2, r3, r7, pc}
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%var = alloca i8, i32 8
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call void @bar(i8* %var)
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ret i32 0
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}
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define void @check_simple_too_big() minsize {
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; CHECK-FNSTART-LABEL: check_simple_too_big:
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; CHECK: push {r7, lr}
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; CHECK: sub sp,
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; ...
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; CHECK: add sp,
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; CHECK: pop {r7, pc}
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%var = alloca i8, i32 64
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call void @bar(i8* %var)
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ret void
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}
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define void @check_vfp_fold() minsize {
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; CHECK-FNSTART-LABEL: check_vfp_fold:
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; CHECK: push {r[[GLOBREG:[0-9]+]], lr}
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; CHECK: vpush {d6, d7, d8, d9}
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; CHECK-NOT: sub sp,
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; ...
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; CHECK-NOT: add sp,
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; CHECK: vpop {d6, d7, d8, d9}
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; CHECK: pop {r[[GLOBREG]], pc}
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; iOS uses aligned NEON stores here, which is convenient since we
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; want to make sure that works too.
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; CHECK-IOS: push {r4, r7, lr}
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; CHECK-IOS: sub.w r4, sp, #16
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; CHECK-IOS: bfc r4, #0, #4
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; CHECK-IOS: mov sp, r4
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; CHECK-IOS: vst1.64 {d8, d9}, [r4:128]
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; CHECK-IOS: sub sp, #16
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; ...
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; CHECK-IOS: add r4, sp, #16
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; CHECK-IOS: vld1.64 {d8, d9}, [r4:128]
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; CHECK-IOS: mov sp, r4
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; CHECK-IOS: pop {r4, r7, pc}
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%var = alloca i8, i32 16
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call void asm "", "r,~{d8},~{d9}"(i8* %var)
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call void @bar(i8* %var)
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ret void
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}
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; This function should use just enough space that the "add sp, sp, ..." could be
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; folded in except that doing so would clobber the value being returned.
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define i64 @check_no_return_clobber() minsize {
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; CHECK-FNSTART-LABEL: check_no_return_clobber:
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; CHECK: push {r1, r2, r3, r4, r5, r6, r7, lr}
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; CHECK-NOT: sub sp,
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; ...
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; CHECK: add sp, #24
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; CHECK: pop {r7, pc}
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%var = alloca i8, i32 20
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call void @bar(i8* %var)
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ret i64 0
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}
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define arm_aapcs_vfpcc double @check_vfp_no_return_clobber() minsize {
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; CHECK-FNSTART-LABEL: check_vfp_no_return_clobber:
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; CHECK: push {r[[GLOBREG:[0-9]+]], lr}
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; CHECK: vpush {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9}
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; CHECK-NOT: sub sp,
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; ...
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; CHECK: add sp, #64
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; CHECK: vpop {d8, d9}
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; CHECK: pop {r[[GLOBREG]], pc}
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%var = alloca i8, i32 64
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%tmp = load %bigVec, %bigVec* @var
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call void @bar(i8* %var)
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store %bigVec %tmp, %bigVec* @var
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ret double 1.0
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}
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@dbl = global double 0.0
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; PR18136: there was a bug determining where the first eligible pop in a
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; basic-block was when the entire block was epilogue code.
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define void @test_fold_point(i1 %tst) minsize {
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; CHECK-FNSTART-LABEL: test_fold_point:
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; Important to check for beginning of basic block, because if it gets
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; if-converted the test is probably no longer checking what it should.
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; CHECK: %end
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; CHECK-NEXT: vpop {d7, d8}
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; CHECK-NEXT: pop {r4, pc}
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; With a guaranteed frame-pointer, we want to make sure that its offset in the
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; push block is correct, even if a few registers have been tacked onto a later
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; vpush (PR18160).
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; CHECK-IOS: push {r4, r7, lr}
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; CHECK-IOS-NEXT: add r7, sp, #4
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; CHECK-IOS-NEXT: vpush {d7, d8}
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; We want some memory so there's a stack adjustment to fold...
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%var = alloca i8, i32 8
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; We want a long-lived floating register so that a callee-saved dN is used and
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; there's both a vpop and a pop.
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%live_val = load double, double* @dbl
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br i1 %tst, label %true, label %end
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true:
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call void @bar(i8* %var)
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store double %live_val, double* @dbl
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br label %end
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end:
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; We want the epilogue to be the only thing in a basic block so that we hit
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; the correct edge-case (first inst in block is correct one to adjust).
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ret void
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}
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define void @test_varsize(...) minsize {
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; CHECK-FNSTART-LABEL: test_varsize:
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; CHECK-T1: sub sp, #16
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; CHECK-T1: push {r5, r6, r7, lr}
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; ...
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; CHECK-T1: pop {r2, r3, r7}
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; CHECK-T1: pop {[[POP_REG:r[0-3]]]}
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; CHECK-T1: add sp, #16
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; CHECK-T1: bx [[POP_REG]]
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; CHECK: sub sp, #16
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; CHECK: push {r5, r6, r7, lr}
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; ...
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; CHECK: pop.w {r2, r3, r7, lr}
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; CHECK: add sp, #16
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; CHECK: bx lr
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%var = alloca i8, i32 8
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call void @llvm.va_start(i8* %var)
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call void @bar(i8* %var)
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ret void
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}
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%"MyClass" = type { i8*, i32, i32, float, float, float, [2 x i8], i32, i32* }
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declare float @foo()
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declare void @bar3()
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declare %"MyClass"* @bar2(%"MyClass"* returned, i16*, i32, float, float, i32, i32, i1 zeroext, i1 zeroext, i32)
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define fastcc float @check_vfp_no_return_clobber2(i16* %r, i16* %chars, i32 %length, i1 zeroext %flag) minsize {
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entry:
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; CHECK-FNSTART-LABEL: check_vfp_no_return_clobber2
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; CHECK-LINUX: vpush {d0, d1, d2, d3, d4, d5, d6, d7, d8}
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; CHECK-NOT: sub sp,
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; ...
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; CHECK-LINUX: add sp
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; CHECK-LINUX: vpop {d8}
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%run = alloca %"MyClass", align 4
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%call = call %"MyClass"* @bar2(%"MyClass"* %run, i16* %chars, i32 %length, float 0.000000e+00, float 0.000000e+00, i32 1, i32 1, i1 zeroext false, i1 zeroext true, i32 3)
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%call1 = call float @foo()
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%cmp = icmp eq %"MyClass"* %run, null
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br i1 %cmp, label %exit, label %if.then
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if.then: ; preds = %entry
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call void @bar3()
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br label %exit
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exit: ; preds = %if.then, %entry
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ret float %call1
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}
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declare void @use_arr(i32*)
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define void @test_fold_reuse() minsize {
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; CHECK-FNSTART-LABEL: test_fold_reuse:
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; CHECK: push.w {r4, r7, r8, lr}
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; CHECK: sub sp, #24
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; [...]
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; CHECK: add sp, #24
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; CHECK: pop.w {r4, r7, r8, pc}
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%arr = alloca i8, i32 24
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call void asm sideeffect "", "~{r8},~{r4}"()
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call void @bar(i8* %arr)
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ret void
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}
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; It doesn't matter what registers this pushes and pops; just make sure
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; it doesn't try to push/pop an illegal register on Thumb1.
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define void @test_long_fn() minsize nounwind optsize {
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; CHECK-FNSTART-LABEL: test_long_fn:
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; CHECK-T1-NOFP: push {r7, lr}
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; CHECK-T1-NOFP: pop {r3, pc}
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entry:
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%z = alloca i32, align 4
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call void asm sideeffect ".space 3000", "r"(i32* nonnull %z)
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ret void
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}
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declare void @llvm.va_start(i8*) nounwind
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