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llvm-mirror/test/CodeGen/ARM/machine-verifier.mir
Eli Friedman 83b587811f [ARM] Add MachineVerifier logic for some Thumb1 instructions.
tMOVr and tPUSH/tPOP/tPOP_RET have register constraints which can't be
expressed in TableGen, so check them explicitly. I've unfortunately run
into issues with both of these recently; hopefully this saves some time
for someone else in the future.

Differential Revision: https://reviews.llvm.org/D59383

llvm-svn: 356303
2019-03-15 21:44:49 +00:00

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# RUN: not llc -mtriple=thumb -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the MIR parser runs the machine verifier after parsing.
--- |
define i32 @inc(i32 %a) {
entry:
ret i32 %a
}
...
---
name: inc
tracksRegLiveness: true
body: |
bb.0.entry:
; CHECK: *** Bad machine code: Unsupported register in Thumb1 push/pop ***
frame-setup tPUSH 14, $noreg, undef $r12, killed $lr, implicit-def $sp, implicit $sp
; CHECK: *** Bad machine code: Non-flag-setting Thumb1 mov is v6-only ***
$r2 = tMOVr killed $r6, 14, $noreg
...