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4152cccce8
If you compile with `-mattr=+mve` (enabling integer MVE instructions but not floating-point ones), then the scalar FP //registers// exist and it's legal to move things in and out of them, load and store them, but it's not legal to do arithmetic on them. In D60708, the calls to `addRegisterClass` in ARMISelLowering that enable use of the scalar FP registers became conditionalised on `Subtarget->hasFPRegs()` instead of `Subtarget->hasVFP2Base()`, so that loads, stores and moves of those registers would work. But I didn't realise that that would also enable all the operations on those types by default. Now, if the target doesn't have basic VFP, we follow up those `addRegisterClass` calls by turning back off all the nontrivial operations you can perform on f32 and f64. That causes several knock-on failures, which are fixed by allowing the `VMOVDcc` and `VMOVScc` instructions to be selected even if all you have is `HasFPRegs`, and adjusting several checks for 'is this a double in a single-precision-only world?' to the more general 'is this any FP type we can't do arithmetic on?'. Between those, the whole of the `float-ops.ll` and `fp16-instructions.ll` tests can now run in MVE-without-FP mode and generate correct-looking code. One odd side effect is that I had to relax the check lines in that test so that they permit test functions like `add_f` to be generated as tailcalls to software FP library functions, instead of ordinary calls. Doing that is entirely legal, but the mystery is why this is the first RUN line that's needed the relaxation: on the usual kind of non-FP target, no tailcalls ever seem to be generated. Going by the llc messages, I think `SoftenFloatResult` must be perturbing the code generation in some way, but that's as much as I can guess. Reviewers: dmgreen, ostannard Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63938 llvm-svn: 364909
297 lines
6.6 KiB
LLVM
297 lines
6.6 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=NONE -check-prefix=NOREGS
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=VFP4-ALL
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=FP-ARMv8
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP4-ALL -check-prefix=VFP4-DP
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; RUN: llc < %s -mtriple=thumbv8.1m.main-none-eabihf -mattr=+mve | FileCheck %s -check-prefix=CHECK -check-prefix=NONE -check-prefix=ONLYREGS
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define float @add_f(float %a, float %b) {
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entry:
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; CHECK-LABEL: add_f:
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; NONE: {{b|bl}} __aeabi_fadd
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; HARD: vadd.f32 s0, s0, s1
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%0 = fadd float %a, %b
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ret float %0
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}
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define double @add_d(double %a, double %b) {
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entry:
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; CHECK-LABEL: add_d:
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; NONE: {{b|bl}} __aeabi_dadd
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; SP: {{b|bl}} __aeabi_dadd
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; DP: vadd.f64 d0, d0, d1
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%0 = fadd double %a, %b
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ret double %0
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}
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define float @sub_f(float %a, float %b) {
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entry:
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; CHECK-LABEL: sub_f:
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; NONE: {{b|bl}} __aeabi_fsub
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; HARD: vsub.f32 s
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%0 = fsub float %a, %b
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ret float %0
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}
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define double @sub_d(double %a, double %b) {
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entry:
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; CHECK-LABEL: sub_d:
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; NONE: {{b|bl}} __aeabi_dsub
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; SP: {{b|bl}} __aeabi_dsub
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; DP: vsub.f64 d0, d0, d1
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%0 = fsub double %a, %b
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ret double %0
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}
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define float @mul_f(float %a, float %b) {
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entry:
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; CHECK-LABEL: mul_f:
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; NONE: {{b|bl}} __aeabi_fmul
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; HARD: vmul.f32 s
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%0 = fmul float %a, %b
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ret float %0
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}
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define double @mul_d(double %a, double %b) {
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entry:
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; CHECK-LABEL: mul_d:
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; NONE: {{b|bl}} __aeabi_dmul
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; SP: {{b|bl}} __aeabi_dmul
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; DP: vmul.f64 d0, d0, d1
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%0 = fmul double %a, %b
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ret double %0
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}
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define float @div_f(float %a, float %b) {
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entry:
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; CHECK-LABEL: div_f:
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; NONE: {{b|bl}} __aeabi_fdiv
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; HARD: vdiv.f32 s
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%0 = fdiv float %a, %b
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ret float %0
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}
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define double @div_d(double %a, double %b) {
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entry:
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; CHECK-LABEL: div_d:
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; NONE: {{b|bl}} __aeabi_ddiv
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; SP: {{b|bl}} __aeabi_ddiv
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; DP: vdiv.f64 d0, d0, d1
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%0 = fdiv double %a, %b
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ret double %0
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}
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define float @rem_f(float %a, float %b) {
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entry:
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; CHECK-LABEL: rem_f:
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; NONE: bl fmodf
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; HARD: b fmodf
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%0 = frem float %a, %b
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ret float %0
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}
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define double @rem_d(double %a, double %b) {
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entry:
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; CHECK-LABEL: rem_d:
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; NONE: bl fmod
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; HARD: b fmod
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%0 = frem double %a, %b
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ret double %0
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}
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define float @load_f(float* %a) {
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entry:
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; CHECK-LABEL: load_f:
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; NONE: ldr r0, [r0]
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; HARD: vldr s0, [r0]
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%0 = load float, float* %a, align 4
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ret float %0
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}
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define double @load_d(double* %a) {
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entry:
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; CHECK-LABEL: load_d:
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; NOREGS: ldm r0, {r0, r1}
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; ONLYREGS: vldr d0, [r0]
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; HARD: vldr d0, [r0]
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%0 = load double, double* %a, align 8
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ret double %0
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}
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define void @store_f(float* %a, float %b) {
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entry:
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; CHECK-LABEL: store_f:
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; NONE: str r1, [r0]
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; HARD: vstr s0, [r0]
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store float %b, float* %a, align 4
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ret void
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}
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define void @store_d(double* %a, double %b) {
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entry:
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; CHECK-LABEL: store_d:
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; NOREGS: strd r2, r3, [r0]
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; ONLYREGS: vstr d0, [r0]
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; HARD: vstr d0, [r0]
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store double %b, double* %a, align 8
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ret void
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}
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define double @f_to_d(float %a) {
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; CHECK-LABEL: f_to_d:
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; NONE: bl __aeabi_f2d
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; SP: bl __aeabi_f2d
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; DP: vcvt.f64.f32 d0, s0
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%1 = fpext float %a to double
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ret double %1
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}
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define float @d_to_f(double %a) {
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; CHECK-LABEL: d_to_f:
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; NONE: bl __aeabi_d2f
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; SP: bl __aeabi_d2f
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; DP: vcvt.f32.f64 s0, d0
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%1 = fptrunc double %a to float
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ret float %1
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}
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define i32 @f_to_si(float %a) {
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; CHECK-LABEL: f_to_si:
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; NONE: bl __aeabi_f2iz
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; HARD: vcvt.s32.f32 s0, s0
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; HARD: vmov r0, s0
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%1 = fptosi float %a to i32
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ret i32 %1
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}
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define i32 @d_to_si(double %a) {
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; CHECK-LABEL: d_to_si:
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; NONE: bl __aeabi_d2iz
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; SP: vmov r0, r1, d0
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; SP: bl __aeabi_d2iz
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; DP: vcvt.s32.f64 s0, d0
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; DP: vmov r0, s0
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%1 = fptosi double %a to i32
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ret i32 %1
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}
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define i32 @f_to_ui(float %a) {
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; CHECK-LABEL: f_to_ui:
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; NONE: bl __aeabi_f2uiz
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; HARD: vcvt.u32.f32 s0, s0
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; HARD: vmov r0, s0
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%1 = fptoui float %a to i32
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ret i32 %1
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}
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define i32 @d_to_ui(double %a) {
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; CHECK-LABEL: d_to_ui:
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; NONE: bl __aeabi_d2uiz
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; SP: vmov r0, r1, d0
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; SP: bl __aeabi_d2uiz
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; DP: vcvt.u32.f64 s0, d0
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; DP: vmov r0, s0
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%1 = fptoui double %a to i32
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ret i32 %1
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}
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define float @si_to_f(i32 %a) {
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; CHECK-LABEL: si_to_f:
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; NONE: bl __aeabi_i2f
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; HARD: vcvt.f32.s32 s0, s0
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%1 = sitofp i32 %a to float
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ret float %1
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}
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define double @si_to_d(i32 %a) {
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; CHECK-LABEL: si_to_d:
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; NONE: bl __aeabi_i2d
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; SP: bl __aeabi_i2d
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; DP: vcvt.f64.s32 d0, s0
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%1 = sitofp i32 %a to double
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ret double %1
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}
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define float @ui_to_f(i32 %a) {
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; CHECK-LABEL: ui_to_f:
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; NONE: bl __aeabi_ui2f
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; HARD: vcvt.f32.u32 s0, s0
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%1 = uitofp i32 %a to float
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ret float %1
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}
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define double @ui_to_d(i32 %a) {
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; CHECK-LABEL: ui_to_d:
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; NONE: bl __aeabi_ui2d
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; SP: bl __aeabi_ui2d
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; DP: vcvt.f64.u32 d0, s0
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%1 = uitofp i32 %a to double
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ret double %1
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}
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define float @bitcast_i_to_f(i32 %a) {
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; CHECK-LABEL: bitcast_i_to_f:
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; NONE-NOT: mov
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; HARD: vmov s0, r0
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%1 = bitcast i32 %a to float
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ret float %1
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}
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define double @bitcast_i_to_d(i64 %a) {
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; CHECK-LABEL: bitcast_i_to_d:
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; NONE-NOT: mov
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; HARD: vmov d0, r0, r1
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%1 = bitcast i64 %a to double
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ret double %1
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}
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define i32 @bitcast_f_to_i(float %a) {
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; CHECK-LABEL: bitcast_f_to_i:
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; NONE-NOT: mov
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; HARD: vmov r0, s0
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%1 = bitcast float %a to i32
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ret i32 %1
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}
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define i64 @bitcast_d_to_i(double %a) {
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; CHECK-LABEL: bitcast_d_to_i:
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; NONE-NOT: mov
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; HARD: vmov r0, r1, d0
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%1 = bitcast double %a to i64
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ret i64 %1
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}
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define float @select_f(float %a, float %b, i1 %c) {
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; CHECK-LABEL: select_f:
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; NOREGS: lsls r2, r2, #31
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; NOREGS: moveq r0, r1
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; ONLYREGS: lsls r2, r2, #31
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; ONLYREGS: vmovne.f32 s2, s0
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; HARD: lsls r0, r0, #31
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; VFP4-ALL: vmovne.f32 s1, s0
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; VFP4-ALL: vmov.f32 s0, s1
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; FP-ARMv8: vseleq.f32 s0, s1, s0
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%1 = select i1 %c, float %a, float %b
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ret float %1
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}
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define double @select_d(double %a, double %b, i1 %c) {
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; CHECK-LABEL: select_d:
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; NONE: ldr{{(.w)?}} [[REG:r[0-9]+]], [sp]
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; NONE ands [[REG]], [[REG]], #1
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; NONE-DAG: moveq r0, r2
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; NONE-DAG: moveq r1, r3
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; SP: ands r0, r0, #1
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; SP-DAG: vmov [[ALO:r[0-9]+]], [[AHI:r[0-9]+]], d0
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; SP-DAG: vmov [[BLO:r[0-9]+]], [[BHI:r[0-9]+]], d1
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; SP: itt ne
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; SP-DAG: movne [[BLO]], [[ALO]]
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; SP-DAG: movne [[BHI]], [[AHI]]
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; SP: vmov d0, [[BLO]], [[BHI]]
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; DP: lsls r0, r0, #31
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; VFP4-DP: vmovne.f64 d1, d0
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; VFP4-DP: vmov.f64 d0, d1
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; FP-ARMV8: vseleq.f64 d0, d1, d0
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%1 = select i1 %c, double %a, double %b
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ret double %1
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}
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