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2a68ddf041
Summary: This patch implements minimal VE code generation for empty function bodies (no args, no value return). Contents * empty function code generation test. * Minimal function prologue & epilogue emission * Instruction formats and instruction definitions as far as required for the empty function prologue & epilogue. * I64 register class definitions. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D72598
51 lines
1.7 KiB
C++
51 lines
1.7 KiB
C++
//===- VETargetTransformInfo.h - VE specific TTI ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// VE target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
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#include "VE.h"
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#include "VETargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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namespace llvm {
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class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
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using BaseT = BasicTTIImplBase<VETTIImpl>;
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friend BaseT;
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const VESubtarget *ST;
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const VETargetLowering *TLI;
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const VESubtarget *getST() const { return ST; }
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const VETargetLowering *getTLI() const { return TLI; }
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public:
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explicit VETTIImpl(const VETargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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unsigned getNumberOfRegisters(unsigned ClassID) const { return 64; }
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unsigned getRegisterBitWidth(bool Vector) const { return 64; }
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unsigned getMinVectorRegisterBitWidth() const { return 64; }
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
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