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This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
58 lines
2.3 KiB
LLVM
58 lines
2.3 KiB
LLVM
; RUN: llc -hexagon-emit-jt-text=true < %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon-unknown--elf"
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; CHECK: .text
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; CHECK-NOT: .rodata
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; CHECK: .word
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@lane0_pwr_st = global i32 0, align 4
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@lane1_pwr_st = global i32 0, align 4
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@lane2_pwr_st = global i32 0, align 4
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@lane3_pwr_st = global i32 0, align 4
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; Function Attrs: noinline nounwind
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define void @test2(i32 %lane_id, i32 %rx_pwr_st) #0 {
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entry:
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%lane_id.addr = alloca i32, align 4
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%rx_pwr_st.addr = alloca i32, align 4
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store i32 %lane_id, i32* %lane_id.addr, align 4
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store i32 %rx_pwr_st, i32* %rx_pwr_st.addr, align 4
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%0 = load i32, i32* %lane_id.addr, align 4
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switch i32 %0, label %sw.epilog [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.bb2
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i32 3, label %sw.bb3
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i32 15, label %sw.bb4
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]
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sw.bb: ; preds = %entry
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store i32 1, i32* @lane0_pwr_st, align 4
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br label %sw.epilog
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sw.bb1: ; preds = %entry
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store i32 1, i32* @lane1_pwr_st, align 4
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br label %sw.epilog
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sw.bb2: ; preds = %entry
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store i32 1, i32* @lane2_pwr_st, align 4
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br label %sw.epilog
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sw.bb3: ; preds = %entry
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store i32 1, i32* @lane3_pwr_st, align 4
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br label %sw.epilog
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sw.bb4: ; preds = %entry
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store i32 1, i32* @lane0_pwr_st, align 4
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store i32 1, i32* @lane1_pwr_st, align 4
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store i32 1, i32* @lane2_pwr_st, align 4
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store i32 1, i32* @lane3_pwr_st, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %entry, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
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ret void
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}
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attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
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