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https://github.com/RPCS3/llvm-mirror.git
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ce9bb052e5
This adds a new subtarget feature called FPARMv8 (implied by NEON), and predicates the support of the FP instructions and registers on this feature. llvm-svn: 193739
198 lines
6.7 KiB
LLVM
198 lines
6.7 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
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%myStruct = type { i64 , i8, i32 }
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@var8 = global i8 0
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@var32 = global i32 0
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@var64 = global i64 0
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@var128 = global i128 0
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@varfloat = global float 0.0
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@vardouble = global double 0.0
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@varstruct = global %myStruct zeroinitializer
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define void @take_i8s(i8 %val1, i8 %val2) {
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; CHECK-LABEL: take_i8s:
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store i8 %val2, i8* @var8
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; Not using w1 may be technically allowed, but it would indicate a
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; problem in itself.
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; CHECK: strb w1, [{{x[0-9]+}}, #:lo12:var8]
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ret void
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}
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define void @add_floats(float %val1, float %val2) {
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; CHECK-LABEL: add_floats:
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%newval = fadd float %val1, %val2
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; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1
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; CHECK-NOFP-NOT: fadd
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store float %newval, float* @varfloat
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; CHECK: str [[ADDRES]], [{{x[0-9]+}}, #:lo12:varfloat]
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ret void
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}
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; byval pointers should be allocated to the stack and copied as if
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; with memcpy.
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define void @take_struct(%myStruct* byval %structval) {
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; CHECK-LABEL: take_struct:
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%addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
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%addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
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%val0 = load volatile i32* %addr0
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; Some weird move means x0 is used for one access
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; CHECK: ldr [[REG32:w[0-9]+]], [{{x[0-9]+|sp}}, #12]
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store volatile i32 %val0, i32* @var32
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; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32]
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%val1 = load volatile i64* %addr1
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; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}]
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store volatile i64 %val1, i64* @var64
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; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
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ret void
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}
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; %structval should be at sp + 16
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define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) {
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; CHECK-LABEL: check_byval_align:
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%addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
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%addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
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%val0 = load volatile i32* %addr0
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; Some weird move means x0 is used for one access
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; CHECK: add x[[STRUCTVAL_ADDR:[0-9]+]], sp, #16
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; CHECK: ldr [[REG32:w[0-9]+]], [x[[STRUCTVAL_ADDR]], #12]
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store i32 %val0, i32* @var32
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; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32]
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%val1 = load volatile i64* %addr1
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; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16]
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store i64 %val1, i64* @var64
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; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64]
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ret void
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}
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define i32 @return_int() {
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; CHECK-LABEL: return_int:
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%val = load i32* @var32
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ret i32 %val
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; CHECK: ldr w0, [{{x[0-9]+}}, #:lo12:var32]
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; Make sure epilogue follows
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; CHECK-NEXT: ret
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}
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define double @return_double() {
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; CHECK-LABEL: return_double:
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ret double 3.14
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; CHECK: ldr d0, [{{x[0-9]+}}, #:lo12:.LCPI
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; CHECK-NOFP-NOT: ldr d0,
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}
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; This is the kind of IR clang will produce for returning a struct
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; small enough to go into registers. Not all that pretty, but it
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; works.
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define [2 x i64] @return_struct() {
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; CHECK-LABEL: return_struct:
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%addr = bitcast %myStruct* @varstruct to [2 x i64]*
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%val = load [2 x i64]* %addr
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ret [2 x i64] %val
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; CHECK: ldr x0, [{{x[0-9]+}}, #:lo12:varstruct]
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; Odd register regex below disallows x0 which we want to be live now.
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; CHECK: add {{x[1-9][0-9]*}}, {{x[1-9][0-9]*}}, #:lo12:varstruct
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; CHECK-NEXT: ldr x1, [{{x[1-9][0-9]*}}, #8]
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; Make sure epilogue immediately follows
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; CHECK-NEXT: ret
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}
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; Large structs are passed by reference (storage allocated by caller
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; to preserve value semantics) in x8. Strictly this only applies to
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; structs larger than 16 bytes, but C semantics can still be provided
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; if LLVM does it to %myStruct too. So this is the simplest check
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define void @return_large_struct(%myStruct* sret %retval) {
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; CHECK-LABEL: return_large_struct:
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%addr0 = getelementptr %myStruct* %retval, i64 0, i32 0
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%addr1 = getelementptr %myStruct* %retval, i64 0, i32 1
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%addr2 = getelementptr %myStruct* %retval, i64 0, i32 2
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store i64 42, i64* %addr0
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store i8 2, i8* %addr1
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store i32 9, i32* %addr2
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; CHECK: str {{x[0-9]+}}, [x8]
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; CHECK: strb {{w[0-9]+}}, [x8, #8]
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; CHECK: str {{w[0-9]+}}, [x8, #12]
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ret void
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}
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; This struct is just too far along to go into registers: (only x7 is
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; available, but it needs two). Also make sure that %stacked doesn't
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; sneak into x7 behind.
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define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45,
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i32* %var6, %myStruct* byval %struct, i32* byval %stacked,
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double %notstacked) {
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; CHECK-LABEL: struct_on_stack:
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%addr = getelementptr %myStruct* %struct, i64 0, i32 0
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%val64 = load volatile i64* %addr
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store volatile i64 %val64, i64* @var64
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; Currently nothing on local stack, so struct should be at sp
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; CHECK: ldr [[VAL64:x[0-9]+]], [sp]
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; CHECK: str [[VAL64]], [{{x[0-9]+}}, #:lo12:var64]
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store volatile double %notstacked, double* @vardouble
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; CHECK-NOT: ldr d0
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; CHECK: str d0, [{{x[0-9]+}}, #:lo12:vardouble
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; CHECK-NOFP-NOT: str d0,
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%retval = load volatile i32* %stacked
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ret i32 %retval
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; CHECK: ldr w0, [sp, #16]
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}
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define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
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float %var4, float %var5, float %var6, float %var7,
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float %var8) {
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; CHECK-LABEL: stacked_fpu:
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store float %var8, float* @varfloat
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; Beware as above: the offset would be different on big-endian
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; machines if the first ldr were changed to use s-registers.
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; CHECK: ldr d[[VALFLOAT:[0-9]+]], [sp]
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; CHECK: str s[[VALFLOAT]], [{{x[0-9]+}}, #:lo12:varfloat]
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ret void
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}
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; 128-bit integer types should be passed in xEVEN, xODD rather than
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; the reverse. In this case x2 and x3. Nothing should use x1.
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define i32 @check_i128_regalign(i32 %val0, i128 %val1, i32 %val2) {
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; CHECK: check_i128_regalign
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store i128 %val1, i128* @var128
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; CHECK: str x2, [{{x[0-9]+}}, #:lo12:var128]
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; CHECK: str x3, [{{x[0-9]+}}, #8]
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ret i32 %val2
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; CHECK: mov x0, x4
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}
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define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
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i32 %val4, i32 %val5, i32 %val6, i32 %val7,
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i32 %stack1, i128 %stack2) {
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; CHECK: check_i128_stackalign
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store i128 %stack2, i128* @var128
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; Nothing local on stack in current codegen, so first stack is 16 away
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; CHECK: add x[[REG:[0-9]+]], sp, #16
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; CHECK: ldr {{x[0-9]+}}, [x[[REG]], #8]
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; Important point is that we address sp+24 for second dword
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; CHECK: ldr {{x[0-9]+}}, [sp, #16]
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ret void
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}
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
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define i32 @test_extern() {
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; CHECK-LABEL: test_extern:
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* undef, i32 undef, i32 4, i1 0)
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; CHECK: bl memcpy
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ret i32 0
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}
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