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ce9bb052e5
This adds a new subtarget feature called FPARMv8 (implied by NEON), and predicates the support of the FP instructions and registers on this feature. llvm-svn: 193739
205 lines
6.4 KiB
LLVM
205 lines
6.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 < %s | FileCheck --check-prefix=CHECK-NOFP %s
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%va_list = type {i8*, i8*, i8*, i32, i32}
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@var = global %va_list zeroinitializer
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declare void @llvm.va_start(i8*)
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define void @test_simple(i32 %n, ...) {
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; CHECK-LABEL: test_simple:
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; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
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; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
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; CHECK: mov x[[FPRBASE:[0-9]+]], sp
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; CHECK: str q7, [x[[FPRBASE]], #112]
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; CHECK: add x[[GPRBASE:[0-9]+]], sp, #[[GPRFROMSP:[0-9]+]]
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; CHECK: str x7, [x[[GPRBASE]], #48]
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; CHECK-NOFP: sub sp, sp, #[[STACKSIZE:[0-9]+]]
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; CHECK-NOFP: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
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; CHECK-NOFP: add x[[GPRBASE:[0-9]+]], sp, #[[GPRFROMSP:[0-9]+]]
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; CHECK-NOFP: str x7, [x[[GPRBASE]], #48]
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; CHECK-NOFP-NOT: str q7,
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; CHECK-NOFP: str x1, [sp, #[[GPRFROMSP]]]
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; Omit the middle ones
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; CHECK: str q0, [sp]
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; CHECK: str x1, [sp, #[[GPRFROMSP]]]
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; CHECK-NOFP-NOT: str q0, [sp]
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%addr = bitcast %va_list* @var to i8*
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call void @llvm.va_start(i8* %addr)
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; CHECK: movn [[VR_OFFS:w[0-9]+]], #127
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; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28]
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; CHECK: movn [[GR_OFFS:w[0-9]+]], #55
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; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24]
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; CHECK: add [[VR_TOP:x[0-9]+]], x[[FPRBASE]], #128
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; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16]
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; CHECK: add [[GR_TOP:x[0-9]+]], x[[GPRBASE]], #56
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; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8]
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; CHECK: add [[STACK:x[0-9]+]], sp, #[[STACKSIZE]]
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; CHECK: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
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; CHECK-NOFP: str wzr, [x[[VA_LIST]], #28]
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; CHECK-NOFP: movn [[GR_OFFS:w[0-9]+]], #55
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; CHECK-NOFP: str [[GR_OFFS]], [x[[VA_LIST]], #24]
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; CHECK-NOFP: add [[GR_TOP:x[0-9]+]], x[[GPRBASE]], #56
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; CHECK-NOFP: str [[GR_TOP]], [x[[VA_LIST]], #8]
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; CHECK-NOFP: add [[STACK:x[0-9]+]], sp, #[[STACKSIZE]]
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; CHECK-NOFP: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
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ret void
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}
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define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
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; CHECK-LABEL: test_fewargs:
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; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
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; CHECK: mov x[[FPRBASE:[0-9]+]], sp
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; CHECK: str q7, [x[[FPRBASE]], #96]
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; CHECK: add x[[GPRBASE:[0-9]+]], sp, #[[GPRFROMSP:[0-9]+]]
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; CHECK: str x7, [x[[GPRBASE]], #32]
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; CHECK-NOFP: sub sp, sp, #[[STACKSIZE:[0-9]+]]
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; CHECK-NOFP-NOT: str q7,
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; CHECK-NOFP: mov x[[GPRBASE:[0-9]+]], sp
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; CHECK-NOFP: str x7, [x[[GPRBASE]], #24]
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; Omit the middle ones
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; CHECK: str q1, [sp]
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; CHECK: str x3, [sp, #[[GPRFROMSP]]]
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; CHECK-NOFP-NOT: str q1, [sp]
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; CHECK-NOFP: str x4, [sp]
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%addr = bitcast %va_list* @var to i8*
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call void @llvm.va_start(i8* %addr)
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; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
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; CHECK: movn [[VR_OFFS:w[0-9]+]], #111
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; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28]
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; CHECK: movn [[GR_OFFS:w[0-9]+]], #39
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; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24]
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; CHECK: add [[VR_TOP:x[0-9]+]], x[[FPRBASE]], #112
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; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16]
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; CHECK: add [[GR_TOP:x[0-9]+]], x[[GPRBASE]], #40
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; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8]
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; CHECK: add [[STACK:x[0-9]+]], sp, #[[STACKSIZE]]
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; CHECK: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
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; CHECK-NOFP: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
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; CHECK-NOFP: str wzr, [x[[VA_LIST]], #28]
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; CHECK-NOFP: movn [[GR_OFFS:w[0-9]+]], #31
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; CHECK-NOFP: str [[GR_OFFS]], [x[[VA_LIST]], #24]
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; CHECK-NOFP: add [[GR_TOP:x[0-9]+]], x[[GPRBASE]], #32
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; CHECK-NOFP: str [[GR_TOP]], [x[[VA_LIST]], #8]
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; CHECK-NOFP: add [[STACK:x[0-9]+]], sp, #[[STACKSIZE]]
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; CHECK-NOFP: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
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ret void
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}
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define void @test_nospare([8 x i64], [8 x float], ...) {
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; CHECK-LABEL: test_nospare:
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%addr = bitcast %va_list* @var to i8*
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call void @llvm.va_start(i8* %addr)
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; CHECK-NOT: sub sp, sp
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; CHECK: mov [[STACK:x[0-9]+]], sp
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; CHECK: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
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; CHECK-NOFP-NOT: sub sp, sp
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; CHECK-NOFP: add [[STACK:x[0-9]+]], sp, #64
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; CHECK-NOFP: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
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ret void
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}
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; If there are non-variadic arguments on the stack (here two i64s) then the
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; __stack field should point just past them.
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define void @test_offsetstack([10 x i64], [3 x float], ...) {
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; CHECK-LABEL: test_offsetstack:
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; CHECK: sub sp, sp, #80
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; CHECK: mov x[[FPRBASE:[0-9]+]], sp
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; CHECK: str q7, [x[[FPRBASE]], #64]
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; CHECK-NOT: str x{{[0-9]+}},
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; CHECK-NOFP-NOT: str q7,
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; CHECK-NOT: str x7,
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; Omit the middle ones
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; CHECK: str q3, [sp]
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%addr = bitcast %va_list* @var to i8*
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call void @llvm.va_start(i8* %addr)
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; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
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; CHECK: movn [[VR_OFFS:w[0-9]+]], #79
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; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28]
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; CHECK: str wzr, [x[[VA_LIST]], #24]
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; CHECK: add [[VR_TOP:x[0-9]+]], x[[FPRBASE]], #80
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; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16]
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; CHECK: add [[STACK:x[0-9]+]], sp, #96
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; CHECK: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
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; CHECK-NOFP: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
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; CHECK-NOFP: add [[STACK:x[0-9]+]], sp, #40
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; CHECK-NOFP: str [[STACK]], [{{x[0-9]+}}, #:lo12:var]
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; CHECK-NOFP: str wzr, [x[[VA_LIST]], #28]
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; CHECK-NOFP: str wzr, [x[[VA_LIST]], #24]
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ret void
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}
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declare void @llvm.va_end(i8*)
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define void @test_va_end() nounwind {
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; CHECK-LABEL: test_va_end:
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; CHECK-NEXT: BB#0
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; CHECK-NOFP: BB#0
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%addr = bitcast %va_list* @var to i8*
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call void @llvm.va_end(i8* %addr)
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ret void
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; CHECK-NEXT: ret
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; CHECK-NOFP-NEXT: ret
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}
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declare void @llvm.va_copy(i8* %dest, i8* %src)
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@second_list = global %va_list zeroinitializer
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define void @test_va_copy() {
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; CHECK-LABEL: test_va_copy:
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%srcaddr = bitcast %va_list* @var to i8*
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%dstaddr = bitcast %va_list* @second_list to i8*
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call void @llvm.va_copy(i8* %dstaddr, i8* %srcaddr)
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; Check beginning and end again:
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; CHECK: ldr [[BLOCK:x[0-9]+]], [{{x[0-9]+}}, #:lo12:var]
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; CHECK: add x[[SRC_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
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; CHECK-NOFP: ldr [[BLOCK:x[0-9]+]], [{{x[0-9]+}}, #:lo12:var]
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; CHECK-NOFP: add x[[SRC_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:var
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; CHECK: str [[BLOCK]], [{{x[0-9]+}}, #:lo12:second_list]
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; CHECK: ldr [[BLOCK:x[0-9]+]], [x[[SRC_LIST]], #24]
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; CHECK: add x[[DEST_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:second_list
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; CHECK: str [[BLOCK]], [x[[DEST_LIST]], #24]
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; CHECK-NOFP: str [[BLOCK]], [{{x[0-9]+}}, #:lo12:second_list]
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; CHECK-NOFP: ldr [[BLOCK:x[0-9]+]], [x[[SRC_LIST]], #24]
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; CHECK-NOFP: add x[[DEST_LIST:[0-9]+]], {{x[0-9]+}}, #:lo12:second_list
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; CHECK-NOFP: str [[BLOCK]], [x[[DEST_LIST]], #24]
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ret void
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; CHECK: ret
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; CHECK-NOFP: ret
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}
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