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https://github.com/RPCS3/llvm-mirror.git
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719b0399a8
since bpf instruction set was introduced people learned to read and understand kernel verifier output whereas llvm asm output stayed obscure and unknown. Convert llvm to emit assembler text similar to kernel to avoid this discrepancy Signed-off-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 287300
89 lines
2.7 KiB
LLVM
89 lines
2.7 KiB
LLVM
; RUN: llc < %s -march=bpfel -show-mc-encoding | FileCheck %s
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; Function Attrs: nounwind uwtable
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define i32 @ld_b(i64 %foo, i64* nocapture %bar, i8* %ctx, i8* %ctx2) #0 {
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%1 = tail call i64 @llvm.bpf.load.byte(i8* %ctx, i64 123) #2
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%2 = add i64 %1, %foo
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%3 = load volatile i64, i64* %bar, align 8
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%4 = add i64 %2, %3
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%5 = tail call i64 @llvm.bpf.load.byte(i8* %ctx2, i64 %foo) #2
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%6 = add i64 %4, %5
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%7 = load volatile i64, i64* %bar, align 8
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%8 = add i64 %6, %7
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%9 = trunc i64 %8 to i32
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ret i32 %9
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; CHECK-LABEL: ld_b:
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; CHECK: r0 = *(u8 *)skb[123]
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; CHECK: r0 = *(u8 *)skb[r
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}
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declare i64 @llvm.bpf.load.byte(i8*, i64) #1
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; Function Attrs: nounwind uwtable
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define i32 @ld_h(i8* %ctx, i8* %ctx2, i32 %foo) #0 {
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%1 = tail call i64 @llvm.bpf.load.half(i8* %ctx, i64 123) #2
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%2 = sext i32 %foo to i64
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%3 = tail call i64 @llvm.bpf.load.half(i8* %ctx2, i64 %2) #2
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%4 = add i64 %3, %1
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%5 = trunc i64 %4 to i32
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ret i32 %5
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; CHECK-LABEL: ld_h:
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; CHECK: r0 = *(u16 *)skb[r
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; CHECK: r0 = *(u16 *)skb[123]
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}
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declare i64 @llvm.bpf.load.half(i8*, i64) #1
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; Function Attrs: nounwind uwtable
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define i32 @ld_w(i8* %ctx, i8* %ctx2, i32 %foo) #0 {
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%1 = tail call i64 @llvm.bpf.load.word(i8* %ctx, i64 123) #2
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%2 = sext i32 %foo to i64
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%3 = tail call i64 @llvm.bpf.load.word(i8* %ctx2, i64 %2) #2
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%4 = add i64 %3, %1
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%5 = trunc i64 %4 to i32
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ret i32 %5
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; CHECK-LABEL: ld_w:
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; CHECK: r0 = *(u32 *)skb[r
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; CHECK: r0 = *(u32 *)skb[123]
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}
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declare i64 @llvm.bpf.load.word(i8*, i64) #1
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define i32 @ld_pseudo() #0 {
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entry:
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%call = tail call i64 @llvm.bpf.pseudo(i64 2, i64 3)
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tail call void @bar(i64 %call, i32 4) #2
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ret i32 0
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; CHECK-LABEL: ld_pseudo:
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; CHECK: ld_pseudo r1, 2, 3 # encoding: [0x18,0x21,0x00,0x00,0x03,0x00
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}
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declare void @bar(i64, i32) #1
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declare i64 @llvm.bpf.pseudo(i64, i64) #2
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define i32 @bswap(i64 %a, i64 %b, i64 %c) #0 {
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entry:
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%0 = tail call i64 @llvm.bswap.i64(i64 %a)
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%conv = trunc i64 %b to i32
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%1 = tail call i32 @llvm.bswap.i32(i32 %conv)
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%conv1 = zext i32 %1 to i64
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%add = add i64 %conv1, %0
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%conv2 = trunc i64 %c to i16
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%2 = tail call i16 @llvm.bswap.i16(i16 %conv2)
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%conv3 = zext i16 %2 to i64
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%add4 = add i64 %add, %conv3
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%conv5 = trunc i64 %add4 to i32
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ret i32 %conv5
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; CHECK-LABEL: bswap:
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; CHECK: bswap64 r1 # encoding: [0xdc,0x01,0x00,0x00,0x40,0x00,0x00,0x00]
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; CHECK: bswap32 r2 # encoding: [0xdc,0x02,0x00,0x00,0x20,0x00,0x00,0x00]
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; CHECK: r2 += r1 # encoding: [0x0f,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
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; CHECK: bswap16 r3 # encoding: [0xdc,0x03,0x00,0x00,0x10,0x00,0x00,0x00]
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; CHECK: r2 += r3 # encoding: [0x0f,0x32,0x00,0x00,0x00,0x00,0x00,0x00]
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}
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declare i64 @llvm.bswap.i64(i64) #1
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declare i32 @llvm.bswap.i32(i32) #1
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declare i16 @llvm.bswap.i16(i16) #1
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