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e81c016153
Summary: These register has different encodings on CI and VI, so we add pseudo FLAT_SCRACTH registers to be used before MC, and subtarget specific registers to be used by the MC layer. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15661 llvm-svn: 256178
34 lines
1.5 KiB
ArmAsm
34 lines
1.5 KiB
ArmAsm
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=SI -check-prefix=GCN %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s | FileCheck -check-prefix=CI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
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// Add a different RUN line for the failing checks, because when stderr and stdout are mixed the
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// order things are printed is not deterministic.
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// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
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s_mov_b64 flat_scratch, -1
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// SI: error: invalid operand for instruction
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// CI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x04,0xe8,0xbe]
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// VI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x01,0xe6,0xbe]
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s_mov_b32 flat_scratch_lo, -1
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// SI: error: invalid operand for instruction
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// CI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x03,0xe8,0xbe]
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// VI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x00,0xe6,0xbe]
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s_mov_b32 flat_scratch_hi, -1
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// SI: error: invalid operand for instruction
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// CI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x03,0xe9,0xbe]
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// VI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x00,0xe7,0xbe]
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s_mov_b64 flat_scratch_lo, -1
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// GCN: error: invalid operand for instruction
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s_mov_b64 flat_scratch_hi, -1
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// GCN: error: invalid operand for instruction
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s_mov_b32 flat_scratch, -1
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// GCN: error: invalid operand for instruction
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