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Or we can generate some illegal instructions. E.g. shrn2 v0.4s, v1.2d, #35. The legal range should be in [1, 16]. llvm-svn: 195941
24 lines
1.0 KiB
LLVM
24 lines
1.0 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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define <2 x float> @test_vfma_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) {
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; CHECK: test_vfma_lane_f32:
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; CHECK: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[{{[0-9]+}}]
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; CHECK: fadd {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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entry:
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%shuffle = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32> <i32 1, i32 1>
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%mul = fmul <2 x float> %shuffle, %b
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%add = fadd <2 x float> %mul, %a
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ret <2 x float> %add
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}
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define <4 x i32> @test_vshrn_not_match(<2 x i32> %a, <2 x i64> %b) {
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; CHECK: test_vshrn_not_match
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; CHECK-NOT: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #35
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%1 = bitcast <2 x i32> %a to <1 x i64>
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%2 = ashr <2 x i64> %b, <i64 35, i64 35>
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%vshrn_n = trunc <2 x i64> %2 to <2 x i32>
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%3 = bitcast <2 x i32> %vshrn_n to <1 x i64>
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%shuffle.i = shufflevector <1 x i64> %1, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
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%4 = bitcast <2 x i64> %shuffle.i to <4 x i32>
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ret <4 x i32> %4
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} |