RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 03:53:04 +02:00
Code Issues Projects Releases Wiki Activity
71b6b2942e
llvm-mirror/test/Bitcode/Inputs/invalid-insert-0-indices.bc
Filipe Cabecinhas e8eb389930 [BitcodeReader] Don't allow INSERTVAL/EXTRACTVAL with 0 indices 
This would trigger an assertion later.

Bug found with AFL fuzz.

llvm-svn: 237494
2015-05-16 00:33:12 +00:00

452 B
Raw History

View Raw