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https://github.com/RPCS3/llvm-mirror.git
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a490793037
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
87 lines
2.8 KiB
C++
87 lines
2.8 KiB
C++
//===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the live stack slot analysis pass. It is analogous to
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// live interval analysis except it's analyzing liveness of stack slots rather
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// than registers.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "livestacks"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <limits>
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using namespace llvm;
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char LiveStacks::ID = 0;
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INITIALIZE_PASS_BEGIN(LiveStacks, "livestacks",
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"Live Stack Slot Analysis", false, false)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_END(LiveStacks, "livestacks",
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"Live Stack Slot Analysis", false, false)
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char &llvm::LiveStacksID = LiveStacks::ID;
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void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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AU.addPreserved<SlotIndexes>();
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AU.addRequiredTransitive<SlotIndexes>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void LiveStacks::releaseMemory() {
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// Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
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VNInfoAllocator.Reset();
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S2IMap.clear();
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S2RCMap.clear();
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}
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bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
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TRI = MF.getTarget().getRegisterInfo();
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// FIXME: No analysis is being done right now. We are relying on the
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// register allocators to provide the information.
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return false;
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}
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LiveInterval &
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LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
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assert(Slot >= 0 && "Spill slot indice must be >= 0");
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SS2IntervalMap::iterator I = S2IMap.find(Slot);
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if (I == S2IMap.end()) {
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I = S2IMap.insert(I, std::make_pair(Slot,
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LiveInterval(TargetRegisterInfo::index2StackSlot(Slot), 0.0F)));
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S2RCMap.insert(std::make_pair(Slot, RC));
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} else {
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// Use the largest common subclass register class.
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const TargetRegisterClass *OldRC = S2RCMap[Slot];
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S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
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}
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return I->second;
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}
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/// print - Implement the dump method.
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void LiveStacks::print(raw_ostream &OS, const Module*) const {
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OS << "********** INTERVALS **********\n";
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for (const_iterator I = begin(), E = end(); I != E; ++I) {
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I->second.print(OS);
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int Slot = I->first;
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const TargetRegisterClass *RC = getIntervalRegClass(Slot);
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if (RC)
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OS << " [" << RC->getName() << "]\n";
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else
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OS << " [Unknown]\n";
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}
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}
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