llvm-mirror

mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00

History

Diana Picus cba6da467a [MIR] Print target-specific constant pools This should enable us to test the generation of target-specific constant pools, e.g. for ARM: constants: - id: 0 value: 'g(GOT_PREL)-(LPC0+8-.)' alignment: 4 isTargetSpecific: true I intend to use this to test PIC support in GlobalISel for ARM. This is difficult to test outside of that context, since the existing MIR tests usually rely on parser support as well, and that seems a bit trickier to add. We could try to add a unit test, but the setup for that seems rather convoluted and overkill. We do test however that the parser reports a nice error when encountering a target-specific constant pool. Differential Revision: https://reviews.llvm.org/D36092 llvm-svn: 309806		2017-08-02 11:09:30 +00:00
..
AArch64	Add an ID field to StackObjects	2017-07-20 21:03:45 +00:00
AMDGPU	AMDGPU: Implement memory model	2017-07-21 21:19:23 +00:00
ARM	[MIR] Print target-specific constant pools	2017-08-02 11:09:30 +00:00
Generic	[RegAllocFast] Add the proper initialize method to use the .mir infrastructure	2017-07-07 19:25:42 +00:00
Hexagon	[Hexagon] Handle Hexagon-specific machine operand target flags in MIR	2017-07-10 18:31:02 +00:00
Mips
NVPTX
PowerPC
X86	[MIR] Print target-specific constant pools	2017-08-02 11:09:30 +00:00
README	Add README describing the intention of test/CodeGen/MIR	2016-12-09 20:16:12 +00:00

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.