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04ae1ab1c3
This patch adds LLVM intrinsics for the dcbt (Data Cache Block Touch), dcbtst (Data Cache Block Touch for Store) and isync (Instruction Synchronize) instructions. The intrinsic for dcbt and dcbst in this patch are named llvm.ppc.dcbt.with.hint and llvm.ppc.dcbtst.with.hint respectively as there already exists an intrinsic for llvm.ppc.dcbt and llvm.ppc.dcbtst. However, the original variants of the intrinsics do not accept the TH immediate field, whereas these variants do. Differential Revision: https://reviews.llvm.org/D79633
68 lines
1.8 KiB
LLVM
68 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr | FileCheck %s
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define void @dcbt_with_hint_test1(i8* %a) {
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; CHECK-LABEL: dcbt_with_hint_test1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: dcbt 0, r3
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; CHECK-NEXT: blr
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entry:
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tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 0)
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ret void
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}
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define void @dcbt_with_hint_test2(i8* %a) {
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; CHECK-LABEL: dcbt_with_hint_test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: dcbt 0, r3, 8
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; CHECK-NEXT: blr
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entry:
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tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 8)
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ret void
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}
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define void @dcbt_with_hint_test3(i8* %a) {
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; CHECK-LABEL: dcbt_with_hint_test3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: dcbt 0, r3, 15
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; CHECK-NEXT: blr
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entry:
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tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 15)
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ret void
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}
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define void @dcbtst_with_hint_test1(i8* %a) {
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; CHECK-LABEL: dcbtst_with_hint_test1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: dcbtst 0, r3
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; CHECK-NEXT: blr
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entry:
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tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 0)
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ret void
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}
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define void @dcbtst_with_hint_test2(i8* %a) {
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; CHECK-LABEL: dcbtst_with_hint_test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: dcbtst 0, r3, 8
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; CHECK-NEXT: blr
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entry:
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tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 8)
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ret void
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}
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define void @dcbtst_with_hint_test3(i8* %a) {
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; CHECK-LABEL: dcbtst_with_hint_test3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: dcbtst 0, r3, 15
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; CHECK-NEXT: blr
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entry:
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tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 15)
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ret void
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}
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declare void @llvm.ppc.dcbt.with.hint(i8*, i32)
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declare void @llvm.ppc.dcbtst.with.hint(i8*, i32)
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