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bb10587376
Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
267 lines
8.3 KiB
LLVM
267 lines
8.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = local_unnamed_addr global i64 0, align 8
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define signext i32 @test_ilesll(i64 %a, i64 %b) {
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; CHECK-LABEL: test_ilesll:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi r5, r4, 63
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; CHECK-NEXT: rldicl r6, r3, 1, 63
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; CHECK-NEXT: subfc r3, r3, r4
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; CHECK-NEXT: adde r3, r5, r6
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_ilesll:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: sradi r5, r4, 63
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; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
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; CHECK-BE-NEXT: subc r3, r4, r3
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; CHECK-BE-NEXT: adde r3, r5, r6
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_ilesll:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: sradi r5, r4, 63
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; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
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; CHECK-LE-NEXT: subc r3, r4, r3
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; CHECK-LE-NEXT: adde r3, r5, r6
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp sle i64 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
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; CHECK-LABEL: test_ilesll_sext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi r5, r4, 63
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; CHECK-NEXT: rldicl r6, r3, 1, 63
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; CHECK-NEXT: subfc r3, r3, r4
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; CHECK-NEXT: adde r3, r5, r6
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_ilesll_sext:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: sradi r5, r4, 63
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; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
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; CHECK-BE-NEXT: subc r3, r4, r3
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; CHECK-BE-NEXT: adde r3, r5, r6
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; CHECK-BE-NEXT: neg r3, r3
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_ilesll_sext:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: sradi r5, r4, 63
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; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
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; CHECK-LE-NEXT: subc r3, r4, r3
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; CHECK-LE-NEXT: adde r3, r5, r6
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; CHECK-LE-NEXT: neg r3, r3
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp sle i64 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define signext i32 @test_ilesll_z(i64 %a) {
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; CHECK-LABEL: test_ilesll_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi r4, r3, -1
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; CHECK-NEXT: or r3, r4, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_ilesll_z:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addi r4, r3, -1
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; CHECK-BE-NEXT: or r3, r4, r3
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; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_ilesll_z:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: addi r4, r3, -1
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; CHECK-LE-NEXT: or r3, r4, r3
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; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp slt i64 %a, 1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define signext i32 @test_ilesll_sext_z(i64 %a) {
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; CHECK-LABEL: test_ilesll_sext_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi r4, r3, -1
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; CHECK-NEXT: or r3, r4, r3
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_ilesll_sext_z:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addi r4, r3, -1
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; CHECK-BE-NEXT: or r3, r4, r3
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; CHECK-BE-NEXT: sradi r3, r3, 63
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_ilesll_sext_z:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: addi r4, r3, -1
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; CHECK-LE-NEXT: or r3, r4, r3
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; CHECK-LE-NEXT: sradi r3, r3, 63
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp slt i64 %a, 1
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define void @test_ilesll_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_ilesll_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi r6, r4, 63
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; CHECK-NEXT: addis r5, r2, glob@toc@ha
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; CHECK-NEXT: subfc r4, r3, r4
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: adde r3, r6, r3
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; CHECK-NEXT: std r3, glob@toc@l(r5)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_ilesll_store:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-BE-NEXT: sradi r6, r4, 63
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; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
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; CHECK-BE-NEXT: subc r4, r4, r3
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; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
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; CHECK-BE-NEXT: adde r3, r6, r3
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; CHECK-BE-NEXT: std r3, 0(r5)
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_ilesll_store:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: sradi r6, r4, 63
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; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
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; CHECK-LE-NEXT: subc r4, r4, r3
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; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
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; CHECK-LE-NEXT: adde r3, r6, r3
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; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp sle i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_ilesll_sext_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_ilesll_sext_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi r6, r4, 63
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; CHECK-NEXT: addis r5, r2, glob@toc@ha
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; CHECK-NEXT: subfc r4, r3, r4
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: adde r3, r6, r3
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: std r3, glob@toc@l(r5)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_ilesll_sext_store:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: sradi r6, r4, 63
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; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-BE-NEXT: subc r4, r4, r3
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; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
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; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-BE-NEXT: adde r3, r6, r3
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; CHECK-BE-NEXT: neg r3, r3
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; CHECK-BE-NEXT: std r3, 0(r4)
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_ilesll_sext_store:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: sradi r6, r4, 63
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; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
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; CHECK-LE-NEXT: subc r4, r4, r3
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; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
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; CHECK-LE-NEXT: adde r3, r6, r3
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; CHECK-LE-NEXT: neg r3, r3
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; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp sle i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_ilesll_z_store(i64 %a) {
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; CHECK-LABEL: test_ilesll_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi r5, r3, -1
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; CHECK-NEXT: addis r4, r2, glob@toc@ha
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; CHECK-NEXT: or r3, r5, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: std r3, glob@toc@l(r4)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_ilesll_z_store:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-BE-NEXT: addi r5, r3, -1
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; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-BE-NEXT: or r3, r5, r3
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; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
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; CHECK-BE-NEXT: std r3, 0(r4)
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_ilesll_z_store:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: addi r5, r3, -1
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; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
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; CHECK-LE-NEXT: or r3, r5, r3
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; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
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; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp slt i64 %a, 1
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_ilesll_sext_z_store(i64 %a) {
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; CHECK-LABEL: test_ilesll_sext_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi r5, r3, -1
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; CHECK-NEXT: addis r4, r2, glob@toc@ha
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; CHECK-NEXT: or r3, r5, r3
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: std r3, glob@toc@l(r4)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: test_ilesll_sext_z_store:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-BE-NEXT: addi r5, r3, -1
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; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-BE-NEXT: or r3, r5, r3
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; CHECK-BE-NEXT: sradi r3, r3, 63
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; CHECK-BE-NEXT: std r3, 0(r4)
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; CHECK-BE-NEXT: blr
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;
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; CHECK-LE-LABEL: test_ilesll_sext_z_store:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: addi r5, r3, -1
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; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
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; CHECK-LE-NEXT: or r3, r5, r3
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; CHECK-LE-NEXT: sradi r3, r3, 63
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; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
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; CHECK-LE-NEXT: blr
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entry:
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%cmp = icmp slt i64 %a, 1
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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