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b4b33a61bf
This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374
53 lines
1.7 KiB
LLVM
53 lines
1.7 KiB
LLVM
; RUN: llc -march=mipsel -mxgot -relocation-model=pic < %s | FileCheck %s -check-prefix=O32
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; RUN: llc -march=mips64el -mcpu=mips64r2 -mxgot -relocation-model=pic < %s | \
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; RUN: FileCheck %s -check-prefix=N64
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@v0 = external global i32
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define void @foo1() nounwind {
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entry:
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; O32-LABEL: foo1:
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; O32: lui $[[R0:[0-9]+]], %got_hi(v0)
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; O32: addu $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}}
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; O32: lw ${{[0-9]+}}, %got_lo(v0)($[[R1]])
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; O32: lui $[[R2:[0-9]+]], %call_hi(foo0)
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; O32: addu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
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; O32: lw ${{[0-9]+}}, %call_lo(foo0)($[[R3]])
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; N64-LABEL: foo1:
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; N64-DAG: lui $[[R0:[0-9]+]], %got_hi(v0)
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; N64-DAG: daddu $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}}
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; N64-DAG: lui $[[R2:[0-9]+]], %call_hi(foo0)
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; N64-DAG: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
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; N64-DAG: ld ${{[0-9]+}}, %got_lo(v0)($[[R1]])
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; N64-DAG: ld ${{[0-9]+}}, %call_lo(foo0)($[[R3]])
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%0 = load i32, i32* @v0, align 4
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tail call void @foo0(i32 %0) nounwind
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ret void
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}
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declare void @foo0(i32)
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; call to external function.
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define void @foo2(i32* nocapture %d, i32* nocapture %s, i32 %n) nounwind {
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entry:
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; O32-LABEL: foo2:
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; O32: lui $[[R2:[0-9]+]], %call_hi(memcpy)
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; O32: addu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
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; O32: lw ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
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; N64-LABEL: foo2:
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; N64: lui $[[R2:[0-9]+]], %call_hi(memcpy)
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; N64: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
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; N64: ld ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
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%0 = bitcast i32* %d to i8*
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%1 = bitcast i32* %s to i8*
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tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* %1, i32 %n, i32 4, i1 false)
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ret void
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}
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
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