Monk Chiang 20dc5d0c2f [RISCV] Define vector widening reduction intrinsic. ... Define vwredsumu/vwredsum/vfwredosum/vfwredsum We work with @rogfer01 from BSC to come out this patch. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Differential Revision: https://reviews.llvm.org/D93807		2020-12-26 21:42:30 +08:00
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AArch64	[CodeGen] Add "noreturn" attirbute to _Unwind_Resume	2020-12-24 18:14:18 +07:00
AMDGPU
ARC
ARM
AVR
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Generic	Moved dwarf_eh_resume.ll from Generic to X86 folder	2020-12-24 20:08:50 +07:00
Hexagon
Inputs
Lanai
Mips
MIR
MSP430
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RISCV	[RISCV] Define vector widening reduction intrinsic.	2020-12-26 21:42:30 +08:00
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SystemZ
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VE
WebAssembly
WinCFGuard
WinEH
X86	Moved dwarf_eh_resume.ll from Generic to X86 folder	2020-12-24 20:08:50 +07:00
XCore