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72fc788f2b
Summary: When we restore an SGPR value from scratch, we first load it into a temporary VGPR and then use v_readlane_b32 to copy the value from the VGPR back into an SGPR. We weren't setting the kill flag on the VGPR in the v_readlane_b32 instruction, so the register scavenger wasn't able to re-use this temp value later. I wasn't able to create a lit test for this. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19744 llvm-svn: 268287
989 lines
34 KiB
C++
989 lines
34 KiB
C++
//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SIRegisterInfo.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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using namespace llvm;
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static unsigned getMaxWaveCountPerSIMD(const MachineFunction &MF) {
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const SIMachineFunctionInfo& MFI = *MF.getInfo<SIMachineFunctionInfo>();
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const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
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unsigned SIMDPerCU = 4;
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unsigned MaxInvocationsPerWave = SIMDPerCU * ST.getWavefrontSize();
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return alignTo(MFI.getMaximumWorkGroupSize(MF), MaxInvocationsPerWave) /
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MaxInvocationsPerWave;
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}
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static unsigned getMaxWorkGroupSGPRCount(const MachineFunction &MF) {
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const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
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unsigned MaxWaveCountPerSIMD = getMaxWaveCountPerSIMD(MF);
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unsigned TotalSGPRCountPerSIMD, AddressableSGPRCount, SGPRUsageAlignment;
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unsigned ReservedSGPRCount;
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if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
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TotalSGPRCountPerSIMD = 800;
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AddressableSGPRCount = 102;
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SGPRUsageAlignment = 16;
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ReservedSGPRCount = 6; // VCC, FLAT_SCRATCH, XNACK
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} else {
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TotalSGPRCountPerSIMD = 512;
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AddressableSGPRCount = 104;
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SGPRUsageAlignment = 8;
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ReservedSGPRCount = 2; // VCC
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}
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unsigned MaxSGPRCount = (TotalSGPRCountPerSIMD / MaxWaveCountPerSIMD);
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MaxSGPRCount = alignDown(MaxSGPRCount, SGPRUsageAlignment);
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if (ST.hasSGPRInitBug())
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MaxSGPRCount = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
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return std::min(MaxSGPRCount - ReservedSGPRCount, AddressableSGPRCount);
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}
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static unsigned getMaxWorkGroupVGPRCount(const MachineFunction &MF) {
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unsigned MaxWaveCountPerSIMD = getMaxWaveCountPerSIMD(MF);
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unsigned TotalVGPRCountPerSIMD = 256;
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unsigned VGPRUsageAlignment = 4;
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return alignDown(TotalVGPRCountPerSIMD / MaxWaveCountPerSIMD,
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VGPRUsageAlignment);
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}
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static bool hasPressureSet(const int *PSets, unsigned PSetID) {
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for (unsigned i = 0; PSets[i] != -1; ++i) {
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if (PSets[i] == (int)PSetID)
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return true;
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}
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return false;
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}
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void SIRegisterInfo::classifyPressureSet(unsigned PSetID, unsigned Reg,
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BitVector &PressureSets) const {
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for (MCRegUnitIterator U(Reg, this); U.isValid(); ++U) {
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const int *PSets = getRegUnitPressureSets(*U);
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if (hasPressureSet(PSets, PSetID)) {
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PressureSets.set(PSetID);
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break;
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}
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}
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}
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SIRegisterInfo::SIRegisterInfo() : AMDGPURegisterInfo(),
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SGPRPressureSets(getNumRegPressureSets()),
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VGPRPressureSets(getNumRegPressureSets()) {
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unsigned NumRegPressureSets = getNumRegPressureSets();
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SGPR32SetID = NumRegPressureSets;
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VGPR32SetID = NumRegPressureSets;
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for (unsigned i = 0; i < NumRegPressureSets; ++i) {
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if (strncmp("SGPR_32", getRegPressureSetName(i), 7) == 0)
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SGPR32SetID = i;
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else if (strncmp("VGPR_32", getRegPressureSetName(i), 7) == 0)
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VGPR32SetID = i;
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classifyPressureSet(i, AMDGPU::SGPR0, SGPRPressureSets);
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classifyPressureSet(i, AMDGPU::VGPR0, VGPRPressureSets);
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}
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assert(SGPR32SetID < NumRegPressureSets &&
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VGPR32SetID < NumRegPressureSets);
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}
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void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
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MCRegAliasIterator R(Reg, this, true);
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for (; R.isValid(); ++R)
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Reserved.set(*R);
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}
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unsigned SIRegisterInfo::reservedPrivateSegmentBufferReg(
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const MachineFunction &MF) const {
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unsigned BaseIdx = alignDown(getMaxWorkGroupSGPRCount(MF), 4) - 4;
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unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
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return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SReg_128RegClass);
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}
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unsigned SIRegisterInfo::reservedPrivateSegmentWaveByteOffsetReg(
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const MachineFunction &MF) const {
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unsigned RegCount = getMaxWorkGroupSGPRCount(MF);
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unsigned Reg;
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// Try to place it in a hole after PrivateSegmentbufferReg.
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if (RegCount & 3) {
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// We cannot put the segment buffer in (Idx - 4) ... (Idx - 1) due to
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// alignment constraints, so we have a hole where can put the wave offset.
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Reg = RegCount - 1;
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} else {
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// We can put the segment buffer in (Idx - 4) ... (Idx - 1) and put the
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// wave offset before it.
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Reg = RegCount - 5;
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}
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return AMDGPU::SGPR_32RegClass.getRegister(Reg);
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}
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BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
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// EXEC_LO and EXEC_HI could be allocated and used as regular register, but
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// this seems likely to result in bugs, so I'm marking them as reserved.
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reserveRegisterTuples(Reserved, AMDGPU::EXEC);
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reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
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// Reserve Trap Handler registers - support is not implemented in Codegen.
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reserveRegisterTuples(Reserved, AMDGPU::TBA);
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reserveRegisterTuples(Reserved, AMDGPU::TMA);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP0_TTMP1);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP2_TTMP3);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP4_TTMP5);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9);
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reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11);
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unsigned MaxWorkGroupSGPRCount = getMaxWorkGroupSGPRCount(MF);
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unsigned MaxWorkGroupVGPRCount = getMaxWorkGroupVGPRCount(MF);
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unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
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unsigned NumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
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for (unsigned i = MaxWorkGroupSGPRCount; i < NumSGPRs; ++i) {
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unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
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reserveRegisterTuples(Reserved, Reg);
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}
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for (unsigned i = MaxWorkGroupVGPRCount; i < NumVGPRs; ++i) {
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unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
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reserveRegisterTuples(Reserved, Reg);
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}
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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unsigned ScratchWaveOffsetReg = MFI->getScratchWaveOffsetReg();
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if (ScratchWaveOffsetReg != AMDGPU::NoRegister) {
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// Reserve 1 SGPR for scratch wave offset in case we need to spill.
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reserveRegisterTuples(Reserved, ScratchWaveOffsetReg);
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}
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unsigned ScratchRSrcReg = MFI->getScratchRSrcReg();
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if (ScratchRSrcReg != AMDGPU::NoRegister) {
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// Reserve 4 SGPRs for the scratch buffer resource descriptor in case we need
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// to spill.
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// TODO: May need to reserve a VGPR if doing LDS spilling.
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reserveRegisterTuples(Reserved, ScratchRSrcReg);
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assert(!isSubRegister(ScratchRSrcReg, ScratchWaveOffsetReg));
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}
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// Reserve VGPRs for trap handler usage if "amdgpu-debugger-reserve-trap-regs"
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// attribute was specified.
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const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
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if (ST.debuggerReserveTrapVGPRs()) {
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unsigned ReservedVGPRFirst =
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MaxWorkGroupVGPRCount - MFI->getDebuggerReserveTrapVGPRCount();
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for (unsigned i = ReservedVGPRFirst; i < MaxWorkGroupVGPRCount; ++i) {
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unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
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reserveRegisterTuples(Reserved, Reg);
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}
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}
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return Reserved;
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}
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unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
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unsigned Idx) const {
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const AMDGPUSubtarget &STI = MF.getSubtarget<AMDGPUSubtarget>();
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// FIXME: We should adjust the max number of waves based on LDS size.
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unsigned SGPRLimit = getNumSGPRsAllowed(STI.getGeneration(),
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STI.getMaxWavesPerCU());
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unsigned VGPRLimit = getNumVGPRsAllowed(STI.getMaxWavesPerCU());
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unsigned VSLimit = SGPRLimit + VGPRLimit;
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if (SGPRPressureSets.test(Idx) && VGPRPressureSets.test(Idx)) {
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// FIXME: This is a hack. We should never be considering the pressure of
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// these since no virtual register should ever have this class.
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return VSLimit;
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}
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if (SGPRPressureSets.test(Idx))
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return SGPRLimit;
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return VGPRLimit;
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}
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bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
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return Fn.getFrameInfo()->hasStackObjects();
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}
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bool
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SIRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
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return MF.getFrameInfo()->hasStackObjects();
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}
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bool SIRegisterInfo::requiresVirtualBaseRegisters(
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const MachineFunction &) const {
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// There are no special dedicated stack or frame pointers.
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return true;
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}
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int64_t SIRegisterInfo::getFrameIndexInstrOffset(const MachineInstr *MI,
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int Idx) const {
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if (!SIInstrInfo::isMUBUF(*MI))
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return 0;
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assert(Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::vaddr) &&
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"Should never see frame index on non-address operand");
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int OffIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::offset);
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return MI->getOperand(OffIdx).getImm();
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}
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bool SIRegisterInfo::needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
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return MI->mayLoadOrStore();
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}
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void SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
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unsigned BaseReg,
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int FrameIdx,
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int64_t Offset) const {
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MachineBasicBlock::iterator Ins = MBB->begin();
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DebugLoc DL; // Defaults to "unknown"
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if (Ins != MBB->end())
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DL = Ins->getDebugLoc();
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MachineFunction *MF = MBB->getParent();
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const AMDGPUSubtarget &Subtarget = MF->getSubtarget<AMDGPUSubtarget>();
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const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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assert(isUInt<27>(Offset) &&
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"Private offset should never exceed maximum private size");
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if (Offset == 0) {
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BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), BaseReg)
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.addFrameIndex(FrameIdx);
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return;
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}
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned UnusedCarry = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_ADD_I32_e64), BaseReg)
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.addReg(UnusedCarry, RegState::Define | RegState::Dead)
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.addImm(Offset)
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.addFrameIndex(FrameIdx);
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}
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void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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int64_t Offset) const {
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MachineBasicBlock *MBB = MI.getParent();
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MachineFunction *MF = MBB->getParent();
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const AMDGPUSubtarget &Subtarget = MF->getSubtarget<AMDGPUSubtarget>();
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const SIInstrInfo *TII
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= static_cast<const SIInstrInfo *>(Subtarget.getInstrInfo());
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#ifndef NDEBUG
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// FIXME: Is it possible to be storing a frame index to itself?
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bool SeenFI = false;
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for (const MachineOperand &MO: MI.operands()) {
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if (MO.isFI()) {
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if (SeenFI)
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llvm_unreachable("should not see multiple frame indices");
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SeenFI = true;
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}
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}
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#endif
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MachineOperand *FIOp = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
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assert(FIOp && FIOp->isFI() && "frame index must be address operand");
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assert(TII->isMUBUF(MI));
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MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset);
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int64_t NewOffset = OffsetOp->getImm() + Offset;
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if (isUInt<12>(NewOffset)) {
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// If we have a legal offset, fold it directly into the instruction.
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FIOp->ChangeToRegister(BaseReg, false);
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OffsetOp->setImm(NewOffset);
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return;
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}
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// The offset is not legal, so we must insert an add of the offset.
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MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned NewReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
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DebugLoc DL = MI.getDebugLoc();
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assert(Offset != 0 && "Non-zero offset expected");
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unsigned UnusedCarry = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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// In the case the instruction already had an immediate offset, here only
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// the requested new offset is added because we are leaving the original
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// immediate in place.
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ADD_I32_e64), NewReg)
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.addReg(UnusedCarry, RegState::Define | RegState::Dead)
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.addImm(Offset)
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.addReg(BaseReg);
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FIOp->ChangeToRegister(NewReg, false);
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}
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bool SIRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
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unsigned BaseReg,
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int64_t Offset) const {
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return SIInstrInfo::isMUBUF(*MI) && isUInt<12>(Offset);
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}
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const TargetRegisterClass *SIRegisterInfo::getPointerRegClass(
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const MachineFunction &MF, unsigned Kind) const {
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// This is inaccurate. It depends on the instruction and address space. The
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// only place where we should hit this is for dealing with frame indexes /
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// private accesses, so this is correct in that case.
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return &AMDGPU::VGPR_32RegClass;
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}
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static unsigned getNumSubRegsForSpillOp(unsigned Op) {
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switch (Op) {
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case AMDGPU::SI_SPILL_S512_SAVE:
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case AMDGPU::SI_SPILL_S512_RESTORE:
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case AMDGPU::SI_SPILL_V512_SAVE:
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case AMDGPU::SI_SPILL_V512_RESTORE:
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return 16;
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case AMDGPU::SI_SPILL_S256_SAVE:
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case AMDGPU::SI_SPILL_S256_RESTORE:
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case AMDGPU::SI_SPILL_V256_SAVE:
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case AMDGPU::SI_SPILL_V256_RESTORE:
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return 8;
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case AMDGPU::SI_SPILL_S128_SAVE:
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case AMDGPU::SI_SPILL_S128_RESTORE:
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case AMDGPU::SI_SPILL_V128_SAVE:
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case AMDGPU::SI_SPILL_V128_RESTORE:
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return 4;
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case AMDGPU::SI_SPILL_V96_SAVE:
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case AMDGPU::SI_SPILL_V96_RESTORE:
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return 3;
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case AMDGPU::SI_SPILL_S64_SAVE:
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case AMDGPU::SI_SPILL_S64_RESTORE:
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case AMDGPU::SI_SPILL_V64_SAVE:
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case AMDGPU::SI_SPILL_V64_RESTORE:
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return 2;
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case AMDGPU::SI_SPILL_S32_SAVE:
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case AMDGPU::SI_SPILL_S32_RESTORE:
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case AMDGPU::SI_SPILL_V32_SAVE:
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case AMDGPU::SI_SPILL_V32_RESTORE:
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return 1;
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default: llvm_unreachable("Invalid spill opcode");
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}
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}
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void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
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unsigned LoadStoreOp,
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unsigned Value,
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unsigned ScratchRsrcReg,
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unsigned ScratchOffset,
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int64_t Offset,
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RegScavenger *RS) const {
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MachineBasicBlock *MBB = MI->getParent();
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MachineFunction *MF = MI->getParent()->getParent();
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const SIInstrInfo *TII =
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static_cast<const SIInstrInfo *>(MF->getSubtarget().getInstrInfo());
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DebugLoc DL = MI->getDebugLoc();
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bool IsStore = TII->get(LoadStoreOp).mayStore();
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bool RanOutOfSGPRs = false;
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bool Scavenged = false;
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unsigned SOffset = ScratchOffset;
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unsigned OriginalImmOffset = Offset;
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unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
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unsigned Size = NumSubRegs * 4;
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if (!isUInt<12>(Offset + Size)) {
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SOffset = AMDGPU::NoRegister;
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// We don't have access to the register scavenger if this function is called
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// during PEI::scavengeFrameVirtualRegs().
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if (RS)
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SOffset = RS->FindUnusedReg(&AMDGPU::SGPR_32RegClass);
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if (SOffset == AMDGPU::NoRegister) {
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// There are no free SGPRs, and since we are in the process of spilling
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// VGPRs too. Since we need a VGPR in order to spill SGPRs (this is true
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// on SI/CI and on VI it is true until we implement spilling using scalar
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// stores), we have no way to free up an SGPR. Our solution here is to
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// add the offset directly to the ScratchOffset register, and then
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// subtract the offset after the spill to return ScratchOffset to it's
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// original value.
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RanOutOfSGPRs = true;
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SOffset = ScratchOffset;
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} else {
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Scavenged = true;
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}
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
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.addReg(ScratchOffset)
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.addImm(Offset);
|
|
Offset = 0;
|
|
}
|
|
|
|
for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += 4) {
|
|
unsigned SubReg = NumSubRegs > 1 ?
|
|
getPhysRegSubReg(Value, &AMDGPU::VGPR_32RegClass, i) :
|
|
Value;
|
|
|
|
unsigned SOffsetRegState = 0;
|
|
if (i + 1 == e && Scavenged)
|
|
SOffsetRegState |= RegState::Kill;
|
|
|
|
BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
|
|
.addReg(SubReg, getDefRegState(!IsStore))
|
|
.addReg(ScratchRsrcReg)
|
|
.addReg(SOffset, SOffsetRegState)
|
|
.addImm(Offset)
|
|
.addImm(0) // glc
|
|
.addImm(0) // slc
|
|
.addImm(0) // tfe
|
|
.addReg(Value, RegState::Implicit | getDefRegState(!IsStore))
|
|
.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
|
|
}
|
|
|
|
if (RanOutOfSGPRs) {
|
|
// Subtract the offset we added to the ScratchOffset register.
|
|
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), ScratchOffset)
|
|
.addReg(ScratchOffset)
|
|
.addImm(OriginalImmOffset);
|
|
}
|
|
}
|
|
|
|
void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
|
int SPAdj, unsigned FIOperandNum,
|
|
RegScavenger *RS) const {
|
|
MachineFunction *MF = MI->getParent()->getParent();
|
|
MachineRegisterInfo &MRI = MF->getRegInfo();
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
|
|
MachineFrameInfo *FrameInfo = MF->getFrameInfo();
|
|
const SIInstrInfo *TII =
|
|
static_cast<const SIInstrInfo *>(MF->getSubtarget().getInstrInfo());
|
|
DebugLoc DL = MI->getDebugLoc();
|
|
|
|
MachineOperand &FIOp = MI->getOperand(FIOperandNum);
|
|
int Index = MI->getOperand(FIOperandNum).getIndex();
|
|
|
|
switch (MI->getOpcode()) {
|
|
// SGPR register spill
|
|
case AMDGPU::SI_SPILL_S512_SAVE:
|
|
case AMDGPU::SI_SPILL_S256_SAVE:
|
|
case AMDGPU::SI_SPILL_S128_SAVE:
|
|
case AMDGPU::SI_SPILL_S64_SAVE:
|
|
case AMDGPU::SI_SPILL_S32_SAVE: {
|
|
unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
|
|
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
|
|
|
|
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
|
|
unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
|
|
&AMDGPU::SGPR_32RegClass, i);
|
|
struct SIMachineFunctionInfo::SpilledReg Spill =
|
|
MFI->getSpilledReg(MF, Index, i);
|
|
|
|
if (Spill.hasReg()) {
|
|
BuildMI(*MBB, MI, DL,
|
|
TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
|
|
Spill.VGPR)
|
|
.addReg(SubReg)
|
|
.addImm(Spill.Lane);
|
|
|
|
// FIXME: Since this spills to another register instead of an actual
|
|
// frame index, we should delete the frame index when all references to
|
|
// it are fixed.
|
|
} else {
|
|
// Spill SGPR to a frame index.
|
|
// FIXME we should use S_STORE_DWORD here for VI.
|
|
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
|
|
.addReg(SubReg);
|
|
|
|
unsigned Size = FrameInfo->getObjectSize(Index);
|
|
unsigned Align = FrameInfo->getObjectAlignment(Index);
|
|
MachinePointerInfo PtrInfo
|
|
= MachinePointerInfo::getFixedStack(*MF, Index);
|
|
MachineMemOperand *MMO
|
|
= MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
|
|
Size, Align);
|
|
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_SAVE))
|
|
.addReg(TmpReg) // src
|
|
.addFrameIndex(Index) // frame_idx
|
|
.addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
|
|
.addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
|
|
.addImm(i * 4) // offset
|
|
.addMemOperand(MMO);
|
|
}
|
|
}
|
|
MI->eraseFromParent();
|
|
break;
|
|
}
|
|
|
|
// SGPR register restore
|
|
case AMDGPU::SI_SPILL_S512_RESTORE:
|
|
case AMDGPU::SI_SPILL_S256_RESTORE:
|
|
case AMDGPU::SI_SPILL_S128_RESTORE:
|
|
case AMDGPU::SI_SPILL_S64_RESTORE:
|
|
case AMDGPU::SI_SPILL_S32_RESTORE: {
|
|
unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
|
|
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
|
|
|
|
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
|
|
unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
|
|
&AMDGPU::SGPR_32RegClass, i);
|
|
struct SIMachineFunctionInfo::SpilledReg Spill =
|
|
MFI->getSpilledReg(MF, Index, i);
|
|
|
|
if (Spill.hasReg()) {
|
|
BuildMI(*MBB, MI, DL,
|
|
TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
|
|
SubReg)
|
|
.addReg(Spill.VGPR)
|
|
.addImm(Spill.Lane)
|
|
.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
|
|
} else {
|
|
// Restore SGPR from a stack slot.
|
|
// FIXME: We should use S_LOAD_DWORD here for VI.
|
|
|
|
unsigned Align = FrameInfo->getObjectAlignment(Index);
|
|
unsigned Size = FrameInfo->getObjectSize(Index);
|
|
|
|
MachinePointerInfo PtrInfo
|
|
= MachinePointerInfo::getFixedStack(*MF, Index);
|
|
|
|
MachineMemOperand *MMO = MF->getMachineMemOperand(
|
|
PtrInfo, MachineMemOperand::MOLoad, Size, Align);
|
|
|
|
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg)
|
|
.addFrameIndex(Index) // frame_idx
|
|
.addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
|
|
.addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
|
|
.addImm(i * 4) // offset
|
|
.addMemOperand(MMO);
|
|
BuildMI(*MBB, MI, DL,
|
|
TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), SubReg)
|
|
.addReg(TmpReg, RegState::Kill)
|
|
.addImm(0)
|
|
.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
|
|
}
|
|
}
|
|
|
|
MI->eraseFromParent();
|
|
break;
|
|
}
|
|
|
|
// VGPR register spill
|
|
case AMDGPU::SI_SPILL_V512_SAVE:
|
|
case AMDGPU::SI_SPILL_V256_SAVE:
|
|
case AMDGPU::SI_SPILL_V128_SAVE:
|
|
case AMDGPU::SI_SPILL_V96_SAVE:
|
|
case AMDGPU::SI_SPILL_V64_SAVE:
|
|
case AMDGPU::SI_SPILL_V32_SAVE:
|
|
buildScratchLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET,
|
|
TII->getNamedOperand(*MI, AMDGPU::OpName::src)->getReg(),
|
|
TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
|
|
TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
|
|
FrameInfo->getObjectOffset(Index) +
|
|
TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS);
|
|
MI->eraseFromParent();
|
|
break;
|
|
case AMDGPU::SI_SPILL_V32_RESTORE:
|
|
case AMDGPU::SI_SPILL_V64_RESTORE:
|
|
case AMDGPU::SI_SPILL_V96_RESTORE:
|
|
case AMDGPU::SI_SPILL_V128_RESTORE:
|
|
case AMDGPU::SI_SPILL_V256_RESTORE:
|
|
case AMDGPU::SI_SPILL_V512_RESTORE: {
|
|
buildScratchLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
|
|
TII->getNamedOperand(*MI, AMDGPU::OpName::dst)->getReg(),
|
|
TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
|
|
TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
|
|
FrameInfo->getObjectOffset(Index) +
|
|
TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS);
|
|
MI->eraseFromParent();
|
|
break;
|
|
}
|
|
|
|
default: {
|
|
int64_t Offset = FrameInfo->getObjectOffset(Index);
|
|
FIOp.ChangeToImmediate(Offset);
|
|
if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
|
|
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
|
|
BuildMI(*MBB, MI, MI->getDebugLoc(),
|
|
TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
|
|
.addImm(Offset);
|
|
FIOp.ChangeToRegister(TmpReg, false, false, true);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
|
|
return getEncodingValue(Reg) & 0xff;
|
|
}
|
|
|
|
// FIXME: This is very slow. It might be worth creating a map from physreg to
|
|
// register class.
|
|
const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
|
|
assert(!TargetRegisterInfo::isVirtualRegister(Reg));
|
|
|
|
static const TargetRegisterClass *const BaseClasses[] = {
|
|
&AMDGPU::VGPR_32RegClass,
|
|
&AMDGPU::SReg_32RegClass,
|
|
&AMDGPU::VReg_64RegClass,
|
|
&AMDGPU::SReg_64RegClass,
|
|
&AMDGPU::VReg_96RegClass,
|
|
&AMDGPU::VReg_128RegClass,
|
|
&AMDGPU::SReg_128RegClass,
|
|
&AMDGPU::VReg_256RegClass,
|
|
&AMDGPU::SReg_256RegClass,
|
|
&AMDGPU::VReg_512RegClass,
|
|
&AMDGPU::SReg_512RegClass,
|
|
&AMDGPU::SCC_CLASSRegClass,
|
|
};
|
|
|
|
for (const TargetRegisterClass *BaseClass : BaseClasses) {
|
|
if (BaseClass->contains(Reg)) {
|
|
return BaseClass;
|
|
}
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
// TODO: It might be helpful to have some target specific flags in
|
|
// TargetRegisterClass to mark which classes are VGPRs to make this trivial.
|
|
bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
|
|
switch (RC->getSize()) {
|
|
case 0: return false;
|
|
case 1: return false;
|
|
case 4:
|
|
return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) != nullptr;
|
|
case 8:
|
|
return getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) != nullptr;
|
|
case 12:
|
|
return getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) != nullptr;
|
|
case 16:
|
|
return getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) != nullptr;
|
|
case 32:
|
|
return getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) != nullptr;
|
|
case 64:
|
|
return getCommonSubClass(&AMDGPU::VReg_512RegClass, RC) != nullptr;
|
|
default:
|
|
llvm_unreachable("Invalid register class size");
|
|
}
|
|
}
|
|
|
|
const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
|
|
const TargetRegisterClass *SRC) const {
|
|
switch (SRC->getSize()) {
|
|
case 4:
|
|
return &AMDGPU::VGPR_32RegClass;
|
|
case 8:
|
|
return &AMDGPU::VReg_64RegClass;
|
|
case 12:
|
|
return &AMDGPU::VReg_96RegClass;
|
|
case 16:
|
|
return &AMDGPU::VReg_128RegClass;
|
|
case 32:
|
|
return &AMDGPU::VReg_256RegClass;
|
|
case 64:
|
|
return &AMDGPU::VReg_512RegClass;
|
|
default:
|
|
llvm_unreachable("Invalid register class size");
|
|
}
|
|
}
|
|
|
|
const TargetRegisterClass *SIRegisterInfo::getEquivalentSGPRClass(
|
|
const TargetRegisterClass *VRC) const {
|
|
switch (VRC->getSize()) {
|
|
case 4:
|
|
return &AMDGPU::SGPR_32RegClass;
|
|
case 8:
|
|
return &AMDGPU::SReg_64RegClass;
|
|
case 16:
|
|
return &AMDGPU::SReg_128RegClass;
|
|
case 32:
|
|
return &AMDGPU::SReg_256RegClass;
|
|
case 64:
|
|
return &AMDGPU::SReg_512RegClass;
|
|
default:
|
|
llvm_unreachable("Invalid register class size");
|
|
}
|
|
}
|
|
|
|
const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
|
|
const TargetRegisterClass *RC, unsigned SubIdx) const {
|
|
if (SubIdx == AMDGPU::NoSubRegister)
|
|
return RC;
|
|
|
|
// We can assume that each lane corresponds to one 32-bit register.
|
|
unsigned Count = countPopulation(getSubRegIndexLaneMask(SubIdx));
|
|
if (isSGPRClass(RC)) {
|
|
switch (Count) {
|
|
case 1:
|
|
return &AMDGPU::SGPR_32RegClass;
|
|
case 2:
|
|
return &AMDGPU::SReg_64RegClass;
|
|
case 4:
|
|
return &AMDGPU::SReg_128RegClass;
|
|
case 8:
|
|
return &AMDGPU::SReg_256RegClass;
|
|
case 16: /* fall-through */
|
|
default:
|
|
llvm_unreachable("Invalid sub-register class size");
|
|
}
|
|
} else {
|
|
switch (Count) {
|
|
case 1:
|
|
return &AMDGPU::VGPR_32RegClass;
|
|
case 2:
|
|
return &AMDGPU::VReg_64RegClass;
|
|
case 3:
|
|
return &AMDGPU::VReg_96RegClass;
|
|
case 4:
|
|
return &AMDGPU::VReg_128RegClass;
|
|
case 8:
|
|
return &AMDGPU::VReg_256RegClass;
|
|
case 16: /* fall-through */
|
|
default:
|
|
llvm_unreachable("Invalid sub-register class size");
|
|
}
|
|
}
|
|
}
|
|
|
|
bool SIRegisterInfo::shouldRewriteCopySrc(
|
|
const TargetRegisterClass *DefRC,
|
|
unsigned DefSubReg,
|
|
const TargetRegisterClass *SrcRC,
|
|
unsigned SrcSubReg) const {
|
|
// We want to prefer the smallest register class possible, so we don't want to
|
|
// stop and rewrite on anything that looks like a subregister
|
|
// extract. Operations mostly don't care about the super register class, so we
|
|
// only want to stop on the most basic of copies between the smae register
|
|
// class.
|
|
//
|
|
// e.g. if we have something like
|
|
// vreg0 = ...
|
|
// vreg1 = ...
|
|
// vreg2 = REG_SEQUENCE vreg0, sub0, vreg1, sub1, vreg2, sub2
|
|
// vreg3 = COPY vreg2, sub0
|
|
//
|
|
// We want to look through the COPY to find:
|
|
// => vreg3 = COPY vreg0
|
|
|
|
// Plain copy.
|
|
return getCommonSubClass(DefRC, SrcRC) != nullptr;
|
|
}
|
|
|
|
unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
|
|
const TargetRegisterClass *SubRC,
|
|
unsigned Channel) const {
|
|
|
|
switch (Reg) {
|
|
case AMDGPU::VCC:
|
|
switch(Channel) {
|
|
case 0: return AMDGPU::VCC_LO;
|
|
case 1: return AMDGPU::VCC_HI;
|
|
default: llvm_unreachable("Invalid SubIdx for VCC"); break;
|
|
}
|
|
|
|
case AMDGPU::TBA:
|
|
switch(Channel) {
|
|
case 0: return AMDGPU::TBA_LO;
|
|
case 1: return AMDGPU::TBA_HI;
|
|
default: llvm_unreachable("Invalid SubIdx for TBA"); break;
|
|
}
|
|
|
|
case AMDGPU::TMA:
|
|
switch(Channel) {
|
|
case 0: return AMDGPU::TMA_LO;
|
|
case 1: return AMDGPU::TMA_HI;
|
|
default: llvm_unreachable("Invalid SubIdx for TMA"); break;
|
|
}
|
|
|
|
case AMDGPU::FLAT_SCR:
|
|
switch (Channel) {
|
|
case 0:
|
|
return AMDGPU::FLAT_SCR_LO;
|
|
case 1:
|
|
return AMDGPU::FLAT_SCR_HI;
|
|
default:
|
|
llvm_unreachable("Invalid SubIdx for FLAT_SCR");
|
|
}
|
|
break;
|
|
|
|
case AMDGPU::EXEC:
|
|
switch (Channel) {
|
|
case 0:
|
|
return AMDGPU::EXEC_LO;
|
|
case 1:
|
|
return AMDGPU::EXEC_HI;
|
|
default:
|
|
llvm_unreachable("Invalid SubIdx for EXEC");
|
|
}
|
|
break;
|
|
}
|
|
|
|
const TargetRegisterClass *RC = getPhysRegClass(Reg);
|
|
// 32-bit registers don't have sub-registers, so we can just return the
|
|
// Reg. We need to have this check here, because the calculation below
|
|
// using getHWRegIndex() will fail with special 32-bit registers like
|
|
// VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
|
|
if (RC->getSize() == 4) {
|
|
assert(Channel == 0);
|
|
return Reg;
|
|
}
|
|
|
|
unsigned Index = getHWRegIndex(Reg);
|
|
return SubRC->getRegister(Index + Channel);
|
|
}
|
|
|
|
bool SIRegisterInfo::opCanUseLiteralConstant(unsigned OpType) const {
|
|
return OpType == AMDGPU::OPERAND_REG_IMM32;
|
|
}
|
|
|
|
bool SIRegisterInfo::opCanUseInlineConstant(unsigned OpType) const {
|
|
if (opCanUseLiteralConstant(OpType))
|
|
return true;
|
|
|
|
return OpType == AMDGPU::OPERAND_REG_INLINE_C;
|
|
}
|
|
|
|
// FIXME: Most of these are flexible with HSA and we don't need to reserve them
|
|
// as input registers if unused. Whether the dispatch ptr is necessary should be
|
|
// easy to detect from used intrinsics. Scratch setup is harder to know.
|
|
unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
|
|
enum PreloadedValue Value) const {
|
|
|
|
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
|
|
const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
|
|
(void)ST;
|
|
switch (Value) {
|
|
case SIRegisterInfo::WORKGROUP_ID_X:
|
|
assert(MFI->hasWorkGroupIDX());
|
|
return MFI->WorkGroupIDXSystemSGPR;
|
|
case SIRegisterInfo::WORKGROUP_ID_Y:
|
|
assert(MFI->hasWorkGroupIDY());
|
|
return MFI->WorkGroupIDYSystemSGPR;
|
|
case SIRegisterInfo::WORKGROUP_ID_Z:
|
|
assert(MFI->hasWorkGroupIDZ());
|
|
return MFI->WorkGroupIDZSystemSGPR;
|
|
case SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET:
|
|
return MFI->PrivateSegmentWaveByteOffsetSystemSGPR;
|
|
case SIRegisterInfo::PRIVATE_SEGMENT_BUFFER:
|
|
assert(ST.isAmdHsaOS() && "Non-HSA ABI currently uses relocations");
|
|
assert(MFI->hasPrivateSegmentBuffer());
|
|
return MFI->PrivateSegmentBufferUserSGPR;
|
|
case SIRegisterInfo::KERNARG_SEGMENT_PTR:
|
|
assert(MFI->hasKernargSegmentPtr());
|
|
return MFI->KernargSegmentPtrUserSGPR;
|
|
case SIRegisterInfo::DISPATCH_ID:
|
|
llvm_unreachable("unimplemented");
|
|
case SIRegisterInfo::FLAT_SCRATCH_INIT:
|
|
assert(MFI->hasFlatScratchInit());
|
|
return MFI->FlatScratchInitUserSGPR;
|
|
case SIRegisterInfo::DISPATCH_PTR:
|
|
assert(MFI->hasDispatchPtr());
|
|
return MFI->DispatchPtrUserSGPR;
|
|
case SIRegisterInfo::QUEUE_PTR:
|
|
assert(MFI->hasQueuePtr());
|
|
return MFI->QueuePtrUserSGPR;
|
|
case SIRegisterInfo::WORKITEM_ID_X:
|
|
assert(MFI->hasWorkItemIDX());
|
|
return AMDGPU::VGPR0;
|
|
case SIRegisterInfo::WORKITEM_ID_Y:
|
|
assert(MFI->hasWorkItemIDY());
|
|
return AMDGPU::VGPR1;
|
|
case SIRegisterInfo::WORKITEM_ID_Z:
|
|
assert(MFI->hasWorkItemIDZ());
|
|
return AMDGPU::VGPR2;
|
|
}
|
|
llvm_unreachable("unexpected preloaded value type");
|
|
}
|
|
|
|
/// \brief Returns a register that is not used at any point in the function.
|
|
/// If all registers are used, then this function will return
|
|
// AMDGPU::NoRegister.
|
|
unsigned SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
|
|
const TargetRegisterClass *RC) const {
|
|
for (unsigned Reg : *RC)
|
|
if (!MRI.isPhysRegUsed(Reg))
|
|
return Reg;
|
|
return AMDGPU::NoRegister;
|
|
}
|
|
|
|
unsigned SIRegisterInfo::getNumVGPRsAllowed(unsigned WaveCount) const {
|
|
switch(WaveCount) {
|
|
case 10: return 24;
|
|
case 9: return 28;
|
|
case 8: return 32;
|
|
case 7: return 36;
|
|
case 6: return 40;
|
|
case 5: return 48;
|
|
case 4: return 64;
|
|
case 3: return 84;
|
|
case 2: return 128;
|
|
default: return 256;
|
|
}
|
|
}
|
|
|
|
unsigned SIRegisterInfo::getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen,
|
|
unsigned WaveCount) const {
|
|
if (gen >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
|
|
switch (WaveCount) {
|
|
case 10: return 80;
|
|
case 9: return 80;
|
|
case 8: return 96;
|
|
default: return 102;
|
|
}
|
|
} else {
|
|
switch(WaveCount) {
|
|
case 10: return 48;
|
|
case 9: return 56;
|
|
case 8: return 64;
|
|
case 7: return 72;
|
|
case 6: return 80;
|
|
case 5: return 96;
|
|
default: return 103;
|
|
}
|
|
}
|
|
}
|
|
|
|
bool SIRegisterInfo::isVGPR(const MachineRegisterInfo &MRI,
|
|
unsigned Reg) const {
|
|
const TargetRegisterClass *RC;
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg))
|
|
RC = MRI.getRegClass(Reg);
|
|
else
|
|
RC = getPhysRegClass(Reg);
|
|
|
|
return hasVGPRs(RC);
|
|
}
|