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556c69a3de
Summary: Normally TargetLowering::expandFixedPointMul would handle SMULFIXSAT with scale zero by using an SMULO to compute the product and determine if saturation is needed (if overflow happened). But if SMULO isn't custom/legal it falls through and uses the same technique, using MULHS/SMUL_LOHI, as used for non-zero scales. Problem was that when checking for overflow (handling saturation) when not using MULO we did not expect to find a zero scale. So we ended up in an assertion when doing APInt::getLowBitsSet(VTSize, Scale - 1) This patch fixes the problem by adding a new special case for how saturation is computed when scale is zero. Reviewers: RKSimon, bevinh, leonardchan, spatel Reviewed By: RKSimon Subscribers: wuzish, nemanjai, hiraditya, MaskRay, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67071 llvm-svn: 371309
53 lines
1.5 KiB
LLVM
53 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=ppc32 | FileCheck %s
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declare i32 @llvm.smul.fix.sat.i32 (i32, i32, i32)
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define i32 @func1(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: func1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis 5, 32767
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; CHECK-NEXT: mulhw. 6, 3, 4
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; CHECK-NEXT: lis 7, -32768
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; CHECK-NEXT: mullw 3, 3, 4
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; CHECK-NEXT: ori 4, 5, 65535
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; CHECK-NEXT: srawi 5, 3, 31
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; CHECK-NEXT: cmplw 1, 6, 5
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; CHECK-NEXT: bc 12, 0, .LBB0_1
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; CHECK-NEXT: b .LBB0_2
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; CHECK-NEXT: .LBB0_1:
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; CHECK-NEXT: addi 4, 7, 0
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: bclr 12, 6, 0
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; CHECK-NEXT: # %bb.3:
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; CHECK-NEXT: ori 3, 4, 0
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; CHECK-NEXT: blr
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%tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 0)
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ret i32 %tmp
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}
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define i32 @func2(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: func2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mulhw. 6, 3, 4
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; CHECK-NEXT: lis 5, 32767
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; CHECK-NEXT: mullw 3, 3, 4
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; CHECK-NEXT: rotlwi 3, 3, 31
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; CHECK-NEXT: ori 4, 5, 65535
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; CHECK-NEXT: rlwimi 3, 6, 31, 0, 0
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; CHECK-NEXT: bc 12, 1, .LBB1_1
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; CHECK-NEXT: b .LBB1_2
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; CHECK-NEXT: .LBB1_1:
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; CHECK-NEXT: addi 3, 4, 0
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: cmpwi 6, -1
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; CHECK-NEXT: lis 4, -32768
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; CHECK-NEXT: bc 12, 0, .LBB1_3
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB1_3:
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; CHECK-NEXT: addi 3, 4, 0
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; CHECK-NEXT: blr
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%tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 1)
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ret i32 %tmp
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}
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