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https://github.com/RPCS3/llvm-mirror.git
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bcf124828a
As discussed in post-commit review in https://reviews.llvm.org/D73501 if the goal of this is to help vectorizer, then we should actually be teaching vectorizer to do this, because right now this rewrite is still budget-limited, which isn't what we'd want. Additionally, while the rest of the patch series was universally profitable, this particular patch is reportedly (https://reviews.llvm.org/D73501#1905171) exposing cost-modeling issues on ARM. So let's just back this particular patch out. Once there's an undo transform, this could be considered for reintegration. This reverts commit 44edc6fd2c63b7db43e13cc8caf1fee79bebdb5f.
126 lines
5.6 KiB
LLVM
126 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -indvars < %s | FileCheck %s
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; Do not rewrite the user outside the loop because we must keep the instruction
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; inside the loop due to store. Rewrite doesn't give us any profit.
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define void @f(i32 %length.i.88, i32 %length.i, i8* %tmp12, i32 %tmp10, i8* %tmp8) {
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; CHECK-LABEL: @f(
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; CHECK-NEXT: not_zero11.preheader:
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; CHECK-NEXT: [[TMP13:%.*]] = icmp ugt i32 [[LENGTH_I:%.*]], [[LENGTH_I_88:%.*]]
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; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 [[LENGTH_I_88]], i32 [[LENGTH_I]]
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; CHECK-NEXT: [[TMP15:%.*]] = icmp sgt i32 [[TMP14]], 0
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; CHECK-NEXT: br i1 [[TMP15]], label [[NOT_ZERO11_PREHEADER1:%.*]], label [[NOT_ZERO11_POSTLOOP:%.*]]
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; CHECK: not_zero11.preheader1:
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; CHECK-NEXT: br label [[NOT_ZERO11:%.*]]
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; CHECK: not_zero11:
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; CHECK-NEXT: [[V_1:%.*]] = phi i32 [ [[TMP22:%.*]], [[NOT_ZERO11]] ], [ 0, [[NOT_ZERO11_PREHEADER1]] ]
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; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[V_1]] to i64
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; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, i8* [[TMP8:%.*]], i64 [[TMP16]]
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; CHECK-NEXT: [[TMP18:%.*]] = load i8, i8* [[TMP17]], align 1
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; CHECK-NEXT: [[TMP19:%.*]] = zext i8 [[TMP18]] to i32
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; CHECK-NEXT: [[TMP20:%.*]] = or i32 [[TMP19]], [[TMP10:%.*]]
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; CHECK-NEXT: [[TMP21:%.*]] = trunc i32 [[TMP20]] to i8
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; CHECK-NEXT: [[ADDR22:%.*]] = getelementptr inbounds i8, i8* [[TMP12:%.*]], i64 [[TMP16]]
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; CHECK-NEXT: store i8 [[TMP21]], i8* [[ADDR22]], align 1
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; CHECK-NEXT: [[TMP22]] = add nuw nsw i32 [[V_1]], 1
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; CHECK-NEXT: [[TMP23:%.*]] = icmp slt i32 [[TMP22]], [[TMP14]]
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; CHECK-NEXT: br i1 [[TMP23]], label [[NOT_ZERO11]], label [[MAIN_EXIT_SELECTOR:%.*]]
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; CHECK: main.exit.selector:
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; CHECK-NEXT: [[TMP22_LCSSA:%.*]] = phi i32 [ [[TMP22]], [[NOT_ZERO11]] ]
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; CHECK-NEXT: [[TMP24:%.*]] = icmp slt i32 [[TMP22_LCSSA]], [[LENGTH_I]]
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; CHECK-NEXT: br i1 [[TMP24]], label [[NOT_ZERO11_POSTLOOP]], label [[LEAVE:%.*]]
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; CHECK: leave:
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; CHECK-NEXT: ret void
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; CHECK: not_zero11.postloop:
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; CHECK-NEXT: ret void
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;
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not_zero11.preheader:
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%tmp13 = icmp ugt i32 %length.i, %length.i.88
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%tmp14 = select i1 %tmp13, i32 %length.i.88, i32 %length.i
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%tmp15 = icmp sgt i32 %tmp14, 0
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br i1 %tmp15, label %not_zero11, label %not_zero11.postloop
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not_zero11:
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%v_1 = phi i32 [ %tmp22, %not_zero11 ], [ 0, %not_zero11.preheader ]
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%tmp16 = zext i32 %v_1 to i64
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%tmp17 = getelementptr inbounds i8, i8* %tmp8, i64 %tmp16
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%tmp18 = load i8, i8* %tmp17, align 1
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%tmp19 = zext i8 %tmp18 to i32
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%tmp20 = or i32 %tmp19, %tmp10
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%tmp21 = trunc i32 %tmp20 to i8
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%addr22 = getelementptr inbounds i8, i8* %tmp12, i64 %tmp16
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store i8 %tmp21, i8* %addr22, align 1
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%tmp22 = add nuw nsw i32 %v_1, 1
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%tmp23 = icmp slt i32 %tmp22, %tmp14
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br i1 %tmp23, label %not_zero11, label %main.exit.selector
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main.exit.selector:
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%tmp24 = icmp slt i32 %tmp22, %length.i
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br i1 %tmp24, label %not_zero11.postloop, label %leave
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leave:
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ret void
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not_zero11.postloop:
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ret void
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}
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; Rewrite the user outside the loop because there is no hard users inside the loop.
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define void @f1(i32 %length.i.88, i32 %length.i, i8* %tmp12, i32 %tmp10, i8* %tmp8) {
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; CHECK-LABEL: @f1(
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; CHECK-NEXT: not_zero11.preheader:
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; CHECK-NEXT: [[TMP13:%.*]] = icmp ugt i32 [[LENGTH_I:%.*]], [[LENGTH_I_88:%.*]]
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; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 [[LENGTH_I_88]], i32 [[LENGTH_I]]
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; CHECK-NEXT: [[TMP15:%.*]] = icmp sgt i32 [[TMP14]], 0
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; CHECK-NEXT: br i1 [[TMP15]], label [[NOT_ZERO11_PREHEADER1:%.*]], label [[NOT_ZERO11_POSTLOOP:%.*]]
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; CHECK: not_zero11.preheader1:
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; CHECK-NEXT: br label [[NOT_ZERO11:%.*]]
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; CHECK: not_zero11:
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; CHECK-NEXT: [[V_1:%.*]] = phi i32 [ [[TMP22:%.*]], [[NOT_ZERO11]] ], [ 0, [[NOT_ZERO11_PREHEADER1]] ]
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; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[V_1]] to i64
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; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, i8* [[TMP8:%.*]], i64 [[TMP16]]
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; CHECK-NEXT: [[TMP18:%.*]] = load i8, i8* [[TMP17]], align 1
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; CHECK-NEXT: [[TMP19:%.*]] = zext i8 [[TMP18]] to i32
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; CHECK-NEXT: [[TMP20:%.*]] = or i32 [[TMP19]], [[TMP10:%.*]]
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; CHECK-NEXT: [[TMP21:%.*]] = trunc i32 [[TMP20]] to i8
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; CHECK-NEXT: [[ADDR22:%.*]] = getelementptr inbounds i8, i8* [[TMP12:%.*]], i64 [[TMP16]]
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; CHECK-NEXT: [[TMP22]] = add nuw nsw i32 [[V_1]], 1
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; CHECK-NEXT: br i1 false, label [[NOT_ZERO11]], label [[MAIN_EXIT_SELECTOR:%.*]]
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; CHECK: main.exit.selector:
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; CHECK-NEXT: [[TMP24:%.*]] = icmp slt i32 [[TMP14]], [[LENGTH_I]]
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; CHECK-NEXT: br i1 [[TMP24]], label [[NOT_ZERO11_POSTLOOP]], label [[LEAVE:%.*]]
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; CHECK: leave:
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; CHECK-NEXT: ret void
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; CHECK: not_zero11.postloop:
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; CHECK-NEXT: ret void
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;
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not_zero11.preheader:
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%tmp13 = icmp ugt i32 %length.i, %length.i.88
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%tmp14 = select i1 %tmp13, i32 %length.i.88, i32 %length.i
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%tmp15 = icmp sgt i32 %tmp14, 0
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br i1 %tmp15, label %not_zero11, label %not_zero11.postloop
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not_zero11:
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%v_1 = phi i32 [ %tmp22, %not_zero11 ], [ 0, %not_zero11.preheader ]
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%tmp16 = zext i32 %v_1 to i64
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%tmp17 = getelementptr inbounds i8, i8* %tmp8, i64 %tmp16
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%tmp18 = load i8, i8* %tmp17, align 1
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%tmp19 = zext i8 %tmp18 to i32
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%tmp20 = or i32 %tmp19, %tmp10
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%tmp21 = trunc i32 %tmp20 to i8
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%addr22 = getelementptr inbounds i8, i8* %tmp12, i64 %tmp16
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%tmp22 = add nuw nsw i32 %v_1, 1
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%tmp23 = icmp slt i32 %tmp22, %tmp14
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br i1 %tmp23, label %not_zero11, label %main.exit.selector
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main.exit.selector:
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%tmp24 = icmp slt i32 %tmp22, %length.i
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br i1 %tmp24, label %not_zero11.postloop, label %leave
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leave:
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ret void
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not_zero11.postloop:
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ret void
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}
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