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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
337 lines
16 KiB
TableGen
337 lines
16 KiB
TableGen
//=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips64r6 instructions.
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//
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//===----------------------------------------------------------------------===//
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// Notes about removals/changes from MIPS32r6:
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// Reencoded: dclo, dclz
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//===----------------------------------------------------------------------===//
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//
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// Instruction Encodings
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//
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//===----------------------------------------------------------------------===//
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class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
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class DAUI_ENC : DAUI_FM;
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class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>;
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class DATI_ENC : REGIMM_FM<OPCODE5_DATI>;
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class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
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class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;
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class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;
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class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>;
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class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>;
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class DLSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_DLSA>;
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class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>;
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class DMODU_ENC : SPECIAL_3R_FM<0b00011, 0b011111>;
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class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b011100>;
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class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011101>;
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class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
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class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b011101>;
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class LDPC_ENC : PCREL18_FM<OPCODE3_LDPC>;
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class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
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class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
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class CRC32D_ENC : SPECIAL3_2R_SZ_CRC<3,0>;
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class CRC32CD_ENC : SPECIAL3_2R_SZ_CRC<3,1>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Descriptions
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//
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//===----------------------------------------------------------------------===//
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class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> {
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dag OutOperandList = (outs GPROpnd:$rs);
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dag InOperandList = (ins GPROpnd:$rt, uimm16_altrelaxed:$imm);
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string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
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string Constraints = "$rs = $rt";
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InstrItinClass Itinerary = itin;
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}
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class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3, II_DALIGN>;
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class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;
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class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;
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class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;
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class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd, II_DBITSWAP>;
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class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd, II_DCLO>;
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class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd, II_DCLZ>;
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class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV, sdiv>;
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class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU, udiv>;
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class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1, II_DLSA>;
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class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, II_DMOD, srem>;
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class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU, urem>;
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class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH, mulhs>;
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class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>;
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class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
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class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
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class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
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class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simmptr, II_LLD>;
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class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
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class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
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class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
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class BGEC64_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR64Opnd>;
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class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>;
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class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>;
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class BNEC64_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR64Opnd>;
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class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>;
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class BLTUC64_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR64Opnd>;
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class BLTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR64Opnd>;
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class BGEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR64Opnd>;
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class BLEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR64Opnd>;
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class BGTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR64Opnd>;
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class BEQZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR64Opnd>;
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class BNEZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR64Opnd>;
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class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
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GPR64Opnd, II_JIALC> {
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bit isCall = 1;
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list<Register> Defs = [RA];
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}
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class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd,
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II_JIC> {
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bit isBarrier = 1;
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bit isTerminator = 1;
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list<Register> Defs = [AT];
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}
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class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>;
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class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
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class JR_HB64_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR64Opnd> {
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bit isBranch = 1;
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bit isIndirectBranch = 1;
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bit hasDelaySlot = 1;
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bit isTerminator=1;
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bit isBarrier=1;
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bit isCTI = 1;
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InstrItinClass Itinerary = II_JR_HB;
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}
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class CRC32D_DESC : CRC_DESC_BASE<"crc32d", GPR32Opnd, II_CRC32D>;
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class CRC32CD_DESC : CRC_DESC_BASE<"crc32cd", GPR32Opnd, II_CRC32CD>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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//
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//===----------------------------------------------------------------------===//
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let AdditionalPredicates = [NotInMicroMips] in {
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let DecoderMethod = "DecodeDAHIDATI" in {
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def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
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def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
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}
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def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
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def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
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def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
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def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
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def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
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def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
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def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
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def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
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def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
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def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
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def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
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def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
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def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
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def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
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def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
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}
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def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
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def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
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let DecoderNamespace = "Mips32r6_64r6_GP64" in {
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def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
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def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
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def JR_HB64_R6 : JR_HB_R6_ENC, JR_HB64_R6_DESC, ISA_MIPS32R6;
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}
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let AdditionalPredicates = [NotInMicroMips],
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DecoderNamespace = "Mips32r6_64r6_PTR64" in {
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def LL64_R6 : LL_R6_ENC, LL64_R6_DESC, PTR_64, ISA_MIPS64R6;
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def SC64_R6 : SC_R6_ENC, SC64_R6_DESC, PTR_64, ISA_MIPS64R6;
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}
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let DecoderNamespace = "Mips32r6_64r6_GP64" in {
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// Jump and Branch Instructions
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def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6, GPR_64;
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def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6, GPR_64;
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def BEQC64 : BEQC_ENC, BEQC64_DESC, ISA_MIPS64R6, GPR_64;
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def BEQZC64 : BEQZC_ENC, BEQZC64_DESC, ISA_MIPS64R6, GPR_64;
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def BGEC64 : BGEC_ENC, BGEC64_DESC, ISA_MIPS64R6, GPR_64;
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def BGEUC64 : BGEUC_ENC, BGEUC64_DESC, ISA_MIPS64R6, GPR_64;
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def BGTZC64 : BGTZC_ENC, BGTZC64_DESC, ISA_MIPS64R6, GPR_64;
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def BLEZC64 : BLEZC_ENC, BLEZC64_DESC, ISA_MIPS64R6, GPR_64;
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def BLTC64 : BLTC_ENC, BLTC64_DESC, ISA_MIPS64R6, GPR_64;
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def BLTUC64 : BLTUC_ENC, BLTUC64_DESC, ISA_MIPS64R6, GPR_64;
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def BNEC64 : BNEC_ENC, BNEC64_DESC, ISA_MIPS64R6, GPR_64;
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def BNEZC64 : BNEZC_ENC, BNEZC64_DESC, ISA_MIPS64R6, GPR_64;
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}
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let DecoderNamespace = "Mips32r6_64r6_BranchZero" in {
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def BLTZC64 : BLTZC_ENC, BLTZC64_DESC, ISA_MIPS64R6, GPR_64;
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def BGEZC64 : BGEZC_ENC, BGEZC64_DESC, ISA_MIPS64R6, GPR_64;
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}
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let AdditionalPredicates = [NotInMicroMips] in {
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def CRC32D : R6MMR6Rel, CRC32D_ENC, CRC32D_DESC, ISA_MIPS64R6, ASE_CRC;
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def CRC32CD : R6MMR6Rel, CRC32CD_ENC, CRC32CD_DESC, ISA_MIPS64R6, ASE_CRC;
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Aliases
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//
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//===----------------------------------------------------------------------===//
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def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
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def : MipsInstAlias<"jrc $rs", (JIC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
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def : MipsInstAlias<"jalrc $rs", (JIALC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
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//===----------------------------------------------------------------------===//
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//
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// Patterns and Pseudo Instructions
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//
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//===----------------------------------------------------------------------===//
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// i64 selects
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def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
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(OR64 (SELNEZ64 i64:$t, i64:$cond),
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(SELEQZ64 i64:$f, i64:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
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(OR64 (SELEQZ64 i64:$t, i64:$cond),
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(SELNEZ64 i64:$f, i64:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
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(OR64 (SELNEZ64 i64:$t, i64:$cond),
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(SELEQZ64 i64:$f, i64:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
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(OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
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(SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
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(OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
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(SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
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ISA_MIPS64R6;
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def : MipsPat<
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(select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
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(OR64 (SELEQZ64 i64:$t,
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(SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
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sub_32)),
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(SELNEZ64 i64:$f,
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(SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
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sub_32)))>,
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ISA_MIPS64R6;
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def : MipsPat<
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(select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
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(OR64 (SELEQZ64 i64:$t,
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(SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
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sub_32)),
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(SELNEZ64 i64:$f,
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(SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
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sub_32)))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
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(SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
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(SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
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(SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
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(SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
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// i64 selects from an i32 comparison
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// One complicating factor here is that bits 32-63 of an i32 are undefined.
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// FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
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// This would allow us to remove the sign-extensions here.
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def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
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(OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
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(SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
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(OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),
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(SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
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(OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
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(SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
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(OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
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immZExt16:$imm))),
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(SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
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immZExt16:$imm))))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
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(OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
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immZExt16:$imm))),
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(SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
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immZExt16:$imm))))>,
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ISA_MIPS64R6;
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def : MipsPat<(select i32:$cond, i64:$t, immz),
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(SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
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(SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),
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(SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select i32:$cond, immz, i64:$f),
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(SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
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(SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
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ISA_MIPS64R6;
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def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
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(SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
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ISA_MIPS64R6;
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// Patterns used for matching away redundant sign extensions.
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// MIPS32 arithmetic instructions sign extend their result implicitly.
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def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(MUL_R6 GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
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def : MipsPat<(i64 (sext (i32 (sdiv GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(DIV GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
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def : MipsPat<(i64 (sext (i32 (udiv GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(DIVU GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
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def : MipsPat<(i64 (sext (i32 (srem GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(MOD GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
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def : MipsPat<(i64 (sext (i32 (urem GPR32:$src, GPR32:$src2)))),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(MODU GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
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// Pseudo instructions
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let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
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NoIndirectJumpGuards] in {
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def TAILCALL64R6REG : TailCallRegR6<JALR64, ZERO_64, GPR64Opnd>, ISA_MIPS64R6;
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def PseudoIndirectBranch64R6 : PseudoIndirectBranchBaseR6<JALR64, ZERO_64,
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GPR64Opnd>,
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ISA_MIPS64R6;
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}
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let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
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UseIndirectJumpsHazard] in {
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def TAILCALLHB64R6REG : TailCallReg<JR_HB64_R6, GPR64Opnd>,
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ISA_MIPS64R6;
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def PseudoIndrectHazardBranch64R6 : PseudoIndirectBranchBase<JR_HB64_R6,
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GPR64Opnd>,
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ISA_MIPS64R6;
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}
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