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bef1acc269
llvm-svn: 325731
90 lines
2.8 KiB
C++
90 lines
2.8 KiB
C++
//==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Hexagon implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "HexagonGenRegisterInfo.inc"
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namespace llvm {
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namespace Hexagon {
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// Generic (pseudo) subreg indices for use with getHexagonSubRegIndex.
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enum { ps_sub_lo = 0, ps_sub_hi = 1 };
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}
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class HexagonRegisterInfo : public HexagonGenRegisterInfo {
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public:
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HexagonRegisterInfo(unsigned HwMode);
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/// Code Generation virtual methods...
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
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const override;
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const override;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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bool enableMultipleCopyHints() const override { return true; }
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void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
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/// Returns true since we may need scavenging for a temporary register
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/// when generating hardware loop instructions.
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bool requiresRegisterScavenging(const MachineFunction &MF) const override {
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return true;
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}
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/// Returns true. Spill code for predicate registers might need an extra
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/// register.
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
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return true;
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}
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/// Returns true if the frame pointer is valid.
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bool useFPForScavengingIndex(const MachineFunction &MF) const override;
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
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return true;
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}
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// Debug information queries.
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unsigned getRARegister() const;
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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unsigned getFrameRegister() const;
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unsigned getStackRegister() const;
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unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
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unsigned GenIdx) const;
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const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF,
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const TargetRegisterClass *RC) const;
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unsigned getFirstCallerSavedNonParamReg() const;
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF,
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unsigned Kind = 0) const override;
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bool isEHReturnCalleeSaveReg(unsigned Reg) const;
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};
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} // end namespace llvm
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#endif
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