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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-25 22:12:57 +02:00
llvm-mirror/test/CodeGen
Reid Kleckner 733508d4e8 [WinEH] Give up on using CSRs across 32-bit invokes for now
The runtime does not restore CSRs when transferring control back to the
function handling the exception. According to the experts on IRC, LLVM's
register allocator has no way to model register clobbers that only
happen on one edge of the CFG. For now, don't worry about trying to use
the meager three CSRs available on 32-bit X86 and just say that such
invokes preserve nothing.

llvm-svn: 241865
2015-07-09 22:09:41 +00:00
..
AArch64 [AArch64] Select SBFIZ or UBFIZ instead of left + right shifts 2015-07-09 14:33:38 +00:00
AMDGPU AMDGPU/SI: Add debugging subtarget feature for DS offsets 2015-07-06 16:01:58 +00:00
ARM Fix test case to unbreak build. 2015-07-07 14:45:12 +00:00
BPF
CPP
Generic llc: Add a 'run-pass' option. 2015-07-06 17:44:26 +00:00
Hexagon [Hexagon] Add support for atomic RMW operations 2015-07-09 14:51:21 +00:00
Inputs
Mips
MIR MIR Parser: Report an error when parsing machine function with an empty body. 2015-07-09 21:21:33 +00:00
MSP430
NVPTX Add tests for the NVPTXLowerAggrCopies pass. 2015-07-08 21:29:28 +00:00
PowerPC Add missing builtins to the PPC back end for ABI compliance (vol. 2) 2015-07-05 06:03:51 +00:00
SPARC [SPARC] Cleanup handling of the Y/ASR registers. 2015-07-08 16:25:12 +00:00
SystemZ
Thumb
Thumb2 ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually test for it 2015-06-24 20:03:27 +00:00
WebAssembly [WebAssembly] Create a CodeGen unittest directory. 2015-07-06 23:14:57 +00:00
WinEH [SEH] Ensure that empty __except blocks have their own BB 2015-07-08 18:08:52 +00:00
X86 [WinEH] Give up on using CSRs across 32-bit invokes for now 2015-07-09 22:09:41 +00:00
XCore