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762c21ab09
This is required because empty strings are not allowed when generating the assembly parser tables. Differential Revision: https://reviews.llvm.org/D98532
127 lines
5.5 KiB
TableGen
127 lines
5.5 KiB
TableGen
//===-- M68kInstrCompiler.td - Pseudos and Patterns ------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file describes the various pseudo instructions used by the compiler,
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/// as well as Pat patterns used during instruction selection.
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ConstantPool, GlobalAddress, ExternalSymbol, and JumpTable
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//===----------------------------------------------------------------------===//
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def : Pat<(i32 (MxWrapper tconstpool :$src)), (MOV32ri tconstpool :$src)>;
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def : Pat<(i32 (MxWrapper tglobaladdr :$src)), (MOV32ri tglobaladdr :$src)>;
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def : Pat<(i32 (MxWrapper texternalsym :$src)), (MOV32ri texternalsym :$src)>;
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def : Pat<(i32 (MxWrapper tjumptable :$src)), (MOV32ri tjumptable :$src)>;
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def : Pat<(i32 (MxWrapper tblockaddress :$src)), (MOV32ri tblockaddress :$src)>;
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def : Pat<(add MxDRD32:$src, (MxWrapper tconstpool:$opd)),
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(ADD32ri MxDRD32:$src, tconstpool:$opd)>;
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def : Pat<(add MxARD32:$src, (MxWrapper tjumptable:$opd)),
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(ADD32ri MxARD32:$src, tjumptable:$opd)>;
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def : Pat<(add MxARD32:$src, (MxWrapper tglobaladdr :$opd)),
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(ADD32ri MxARD32:$src, tglobaladdr:$opd)>;
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def : Pat<(add MxARD32:$src, (MxWrapper texternalsym:$opd)),
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(ADD32ri MxARD32:$src, texternalsym:$opd)>;
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def : Pat<(add MxARD32:$src, (MxWrapper tblockaddress:$opd)),
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(ADD32ri MxARD32:$src, tblockaddress:$opd)>;
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def : Pat<(store (i32 (MxWrapper tglobaladdr:$src)), iPTR:$dst),
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(MOV32ji MxARI32:$dst, tglobaladdr:$src)>;
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def : Pat<(store (i32 (MxWrapper texternalsym:$src)), iPTR:$dst),
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(MOV32ji MxARI32:$dst, texternalsym:$src)>;
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def : Pat<(store (i32 (MxWrapper tblockaddress:$src)), iPTR:$dst),
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(MOV32ji MxARI32:$dst, tblockaddress:$src)>;
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def : Pat<(i32 (MxWrapperPC tconstpool :$src)), (LEA32q tconstpool :$src)>;
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def : Pat<(i32 (MxWrapperPC tglobaladdr :$src)), (LEA32q tglobaladdr :$src)>;
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def : Pat<(i32 (MxWrapperPC texternalsym :$src)), (LEA32q texternalsym :$src)>;
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def : Pat<(i32 (MxWrapperPC tjumptable :$src)), (LEA32q tjumptable :$src)>;
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def : Pat<(i32 (MxWrapperPC tblockaddress :$src)), (LEA32q tblockaddress :$src)>;
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//===----------------------------------------------------------------------===//
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// Conditional Move Pseudo Instructions
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//
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// CMOV* - Used to implement the SELECT DAG operation. Expanded after
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// instruction selection into a branch sequence.
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//===----------------------------------------------------------------------===//
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let usesCustomInserter = 1, Uses = [CCR] in
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class MxCMove<MxType TYPE>
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: MxPseudo<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$t, TYPE.ROp:$f, i8imm:$cond),
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[(set TYPE.VT:$dst,
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(TYPE.VT (MxCmov TYPE.VT:$t, TYPE.VT:$f, imm:$cond, CCR)))]>;
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def CMOV8d : MxCMove<MxType8d>;
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def CMOV16d : MxCMove<MxType16d>;
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def CMOV32r : MxCMove<MxType32r>;
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//===----------------------------------------------------------------------===//
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// Calls
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//===----------------------------------------------------------------------===//
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// ADJCALLSTACKDOWN/UP implicitly use/def %SP because they may be expanded into
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// a stack adjustment and the codegen must know that they may modify the stack
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// pointer before prolog-epilog rewriting occurs.
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// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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// sub / add which can clobber CCR.
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let Defs = [SP, CCR], Uses = [SP] in {
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def ADJCALLSTACKDOWN
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: MxPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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[(MxCallSeqStart timm:$amt1, timm:$amt2)]>;
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def ADJCALLSTACKUP
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: MxPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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[(MxCallSeqEnd timm:$amt1, timm:$amt2)]>;
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} // Defs
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//===----------------------------------------------------------------------===//
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// Tail Call
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//===----------------------------------------------------------------------===//
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// Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
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// can never use callee-saved registers. That is the purpose of the XR32_TC
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// register classes.
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// FIXME TC is disabled for PIC mode because the global base
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// register which is part of the address mode may be assigned a
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// callee-saved register.
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def : Pat<(MxTCRet (load MxCP_ARII:$dst), imm:$adj),
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(TCRETURNj (MOV32af_TC MxARII32:$dst), imm:$adj)>,
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Requires<[IsNotPIC]>;
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def : Pat<(MxTCRet AR32_TC:$dst, imm:$adj),
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(TCRETURNj MxARI32_TC:$dst, imm:$adj)>;
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def : Pat<(MxTCRet (i32 tglobaladdr:$dst), imm:$adj),
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(TCRETURNq MxPCD32:$dst, imm:$adj)>;
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def : Pat<(MxTCRet (i32 texternalsym:$dst), imm:$adj),
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(TCRETURNq MxPCD32:$dst, imm:$adj)>;
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//===----------------------------------------------------------------------===//
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// Segmented Stack
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//
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// When using segmented stacks these are lowered into instructions which first
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// check if the current stacklet has enough free memory. If it does, memory is
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// allocated by bumping the stack pointer. Otherwise memory is allocated from
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// the heap.
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//===----------------------------------------------------------------------===//
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let Defs = [SP, CCR], Uses = [SP] in
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let usesCustomInserter = 1 in
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def SALLOCA : MxPseudo<(outs MxARD32:$dst), (ins MxARD32:$size),
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[(set iPTR:$dst, (MxSegAlloca iPTR:$size))]>;
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