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203 lines
7.6 KiB
C++
203 lines
7.6 KiB
C++
//===--- AMDHSAKernelDescriptor.h -----------------------------*- C++ -*---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// AMDHSA kernel descriptor definitions. For more information, visit
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/// https://llvm.org/docs/AMDGPUUsage.html#kernel-descriptor
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_AMDHSAKERNELDESCRIPTOR_H
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#define LLVM_SUPPORT_AMDHSAKERNELDESCRIPTOR_H
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#include <cstddef>
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#include <cstdint>
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// Gets offset of specified member in specified type.
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#ifndef offsetof
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#define offsetof(TYPE, MEMBER) ((size_t)&((TYPE*)0)->MEMBER)
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#endif // offsetof
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// Creates enumeration entries used for packing bits into integers. Enumeration
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// entries include bit shift amount, bit width, and bit mask.
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#ifndef AMDHSA_BITS_ENUM_ENTRY
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#define AMDHSA_BITS_ENUM_ENTRY(NAME, SHIFT, WIDTH) \
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NAME ## _SHIFT = (SHIFT), \
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NAME ## _WIDTH = (WIDTH), \
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NAME = (((1 << (WIDTH)) - 1) << (SHIFT))
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#endif // AMDHSA_BITS_ENUM_ENTRY
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// Gets bits for specified bit mask from specified source.
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#ifndef AMDHSA_BITS_GET
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#define AMDHSA_BITS_GET(SRC, MSK) ((SRC & MSK) >> MSK ## _SHIFT)
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#endif // AMDHSA_BITS_GET
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// Sets bits for specified bit mask in specified destination.
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#ifndef AMDHSA_BITS_SET
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#define AMDHSA_BITS_SET(DST, MSK, VAL) \
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DST &= ~MSK; \
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DST |= ((VAL << MSK ## _SHIFT) & MSK)
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#endif // AMDHSA_BITS_SET
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namespace llvm {
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namespace amdhsa {
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// Floating point rounding modes. Must match hardware definition.
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enum : uint8_t {
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FLOAT_ROUND_MODE_NEAR_EVEN = 0,
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FLOAT_ROUND_MODE_PLUS_INFINITY = 1,
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FLOAT_ROUND_MODE_MINUS_INFINITY = 2,
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FLOAT_ROUND_MODE_ZERO = 3,
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};
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// Floating point denorm modes. Must match hardware definition.
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enum : uint8_t {
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FLOAT_DENORM_MODE_FLUSH_SRC_DST = 0,
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FLOAT_DENORM_MODE_FLUSH_DST = 1,
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FLOAT_DENORM_MODE_FLUSH_SRC = 2,
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FLOAT_DENORM_MODE_FLUSH_NONE = 3,
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};
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// System VGPR workitem IDs. Must match hardware definition.
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enum : uint8_t {
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SYSTEM_VGPR_WORKITEM_ID_X = 0,
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SYSTEM_VGPR_WORKITEM_ID_X_Y = 1,
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SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = 2,
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SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = 3,
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};
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// Compute program resource register 1. Must match hardware definition.
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#define COMPUTE_PGM_RSRC1(NAME, SHIFT, WIDTH) \
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AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_ ## NAME, SHIFT, WIDTH)
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enum : int32_t {
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COMPUTE_PGM_RSRC1(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),
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COMPUTE_PGM_RSRC1(GRANULATED_WAVEFRONT_SGPR_COUNT, 6, 4),
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COMPUTE_PGM_RSRC1(PRIORITY, 10, 2),
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COMPUTE_PGM_RSRC1(FLOAT_ROUND_MODE_32, 12, 2),
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COMPUTE_PGM_RSRC1(FLOAT_ROUND_MODE_16_64, 14, 2),
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COMPUTE_PGM_RSRC1(FLOAT_DENORM_MODE_32, 16, 2),
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COMPUTE_PGM_RSRC1(FLOAT_DENORM_MODE_16_64, 18, 2),
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COMPUTE_PGM_RSRC1(PRIV, 20, 1),
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COMPUTE_PGM_RSRC1(ENABLE_DX10_CLAMP, 21, 1),
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COMPUTE_PGM_RSRC1(DEBUG_MODE, 22, 1),
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COMPUTE_PGM_RSRC1(ENABLE_IEEE_MODE, 23, 1),
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COMPUTE_PGM_RSRC1(BULKY, 24, 1),
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COMPUTE_PGM_RSRC1(CDBG_USER, 25, 1),
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COMPUTE_PGM_RSRC1(FP16_OVFL, 26, 1), // GFX9+
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COMPUTE_PGM_RSRC1(RESERVED0, 27, 2),
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COMPUTE_PGM_RSRC1(WGP_MODE, 29, 1), // GFX10+
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COMPUTE_PGM_RSRC1(MEM_ORDERED, 30, 1), // GFX10+
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COMPUTE_PGM_RSRC1(FWD_PROGRESS, 31, 1), // GFX10+
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};
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#undef COMPUTE_PGM_RSRC1
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// Compute program resource register 2. Must match hardware definition.
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#define COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH) \
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AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_ ## NAME, SHIFT, WIDTH)
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enum : int32_t {
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COMPUTE_PGM_RSRC2(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1),
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COMPUTE_PGM_RSRC2(USER_SGPR_COUNT, 1, 5),
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COMPUTE_PGM_RSRC2(ENABLE_TRAP_HANDLER, 6, 1),
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COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_X, 7, 1),
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COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_Y, 8, 1),
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COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_Z, 9, 1),
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COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_INFO, 10, 1),
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COMPUTE_PGM_RSRC2(ENABLE_VGPR_WORKITEM_ID, 11, 2),
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COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_ADDRESS_WATCH, 13, 1),
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COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_MEMORY, 14, 1),
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COMPUTE_PGM_RSRC2(GRANULATED_LDS_SIZE, 15, 9),
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COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, 24, 1),
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COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_FP_DENORMAL_SOURCE, 25, 1),
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COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, 26, 1),
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COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW, 27, 1),
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COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW, 28, 1),
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COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_INEXACT, 29, 1),
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COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO, 30, 1),
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COMPUTE_PGM_RSRC2(RESERVED0, 31, 1),
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};
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#undef COMPUTE_PGM_RSRC2
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// Compute program resource register 3. Must match hardware definition.
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#define COMPUTE_PGM_RSRC3(NAME, SHIFT, WIDTH) \
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AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_ ## NAME, SHIFT, WIDTH)
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enum : int32_t {
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COMPUTE_PGM_RSRC3(SHARED_VGPR_COUNT, 0, 4), // GFX10+
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COMPUTE_PGM_RSRC3(RESERVED0, 4, 28),
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};
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#undef COMPUTE_PGM_RSRC3
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// Kernel code properties. Must be kept backwards compatible.
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#define KERNEL_CODE_PROPERTY(NAME, SHIFT, WIDTH) \
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AMDHSA_BITS_ENUM_ENTRY(KERNEL_CODE_PROPERTY_ ## NAME, SHIFT, WIDTH)
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enum : int32_t {
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KERNEL_CODE_PROPERTY(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),
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KERNEL_CODE_PROPERTY(ENABLE_SGPR_DISPATCH_PTR, 1, 1),
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KERNEL_CODE_PROPERTY(ENABLE_SGPR_QUEUE_PTR, 2, 1),
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KERNEL_CODE_PROPERTY(ENABLE_SGPR_KERNARG_SEGMENT_PTR, 3, 1),
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KERNEL_CODE_PROPERTY(ENABLE_SGPR_DISPATCH_ID, 4, 1),
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KERNEL_CODE_PROPERTY(ENABLE_SGPR_FLAT_SCRATCH_INIT, 5, 1),
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KERNEL_CODE_PROPERTY(ENABLE_SGPR_PRIVATE_SEGMENT_SIZE, 6, 1),
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KERNEL_CODE_PROPERTY(RESERVED0, 7, 3),
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KERNEL_CODE_PROPERTY(ENABLE_WAVEFRONT_SIZE32, 10, 1), // GFX10+
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KERNEL_CODE_PROPERTY(RESERVED1, 11, 5),
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};
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#undef KERNEL_CODE_PROPERTY
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// Kernel descriptor. Must be kept backwards compatible.
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struct kernel_descriptor_t {
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uint32_t group_segment_fixed_size;
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uint32_t private_segment_fixed_size;
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uint8_t reserved0[8];
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int64_t kernel_code_entry_byte_offset;
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uint8_t reserved1[20];
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uint32_t compute_pgm_rsrc3; // GFX10+
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uint32_t compute_pgm_rsrc1;
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uint32_t compute_pgm_rsrc2;
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uint16_t kernel_code_properties;
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uint8_t reserved2[6];
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};
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static_assert(
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sizeof(kernel_descriptor_t) == 64,
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"invalid size for kernel_descriptor_t");
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static_assert(
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offsetof(kernel_descriptor_t, group_segment_fixed_size) == 0,
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"invalid offset for group_segment_fixed_size");
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static_assert(
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offsetof(kernel_descriptor_t, private_segment_fixed_size) == 4,
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"invalid offset for private_segment_fixed_size");
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static_assert(
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offsetof(kernel_descriptor_t, reserved0) == 8,
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"invalid offset for reserved0");
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static_assert(
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offsetof(kernel_descriptor_t, kernel_code_entry_byte_offset) == 16,
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"invalid offset for kernel_code_entry_byte_offset");
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static_assert(
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offsetof(kernel_descriptor_t, reserved1) == 24,
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"invalid offset for reserved1");
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static_assert(
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offsetof(kernel_descriptor_t, compute_pgm_rsrc3) == 44,
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"invalid offset for compute_pgm_rsrc3");
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static_assert(
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offsetof(kernel_descriptor_t, compute_pgm_rsrc1) == 48,
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"invalid offset for compute_pgm_rsrc1");
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static_assert(
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offsetof(kernel_descriptor_t, compute_pgm_rsrc2) == 52,
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"invalid offset for compute_pgm_rsrc2");
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static_assert(
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offsetof(kernel_descriptor_t, kernel_code_properties) == 56,
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"invalid offset for kernel_code_properties");
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static_assert(
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offsetof(kernel_descriptor_t, reserved2) == 58,
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"invalid offset for reserved2");
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} // end namespace amdhsa
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} // end namespace llvm
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#endif // LLVM_SUPPORT_AMDHSAKERNELDESCRIPTOR_H
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