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ba1b1937ee
This adds some extra RUN lines to existing test files, to check that things that worked in previous architecture versions haven't accidentally stopped working in 8.1-M. Also we add some new tests: a test of scalar floating point instructions that could be easily confused with the similar-looking vector ones at assembly time, a test of basic load/store/move access to the FP registers (which has to work even in integer-only MVE); and one final check of the really obvious case where turning off MVE should make sure MVE instructions really are rejected. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62682 llvm-svn: 364293
141 lines
5.2 KiB
ArmAsm
141 lines
5.2 KiB
ArmAsm
@ RUN: llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp -mattr=+fp64 -show-encoding < %s \
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@ RUN: | FileCheck --check-prefix=CHECK-V81M %s
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@ RUN: llvm-mc -triple thumbv8.1m.main -mattr=+fp-armv8 -mattr=+fp64 -show-encoding < %s \
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@ RUN: | FileCheck --check-prefix=CHECK-V81M %s
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@ VCVT{B,T}
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vcvtt.f64.f16 d3, s1
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@ CHECK-V81M: vcvtt.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
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vcvtt.f16.f64 s5, d12
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@ CHECK-V81M: vcvtt.f16.f64 s5, d12 @ encoding: [0xf3,0xee,0xcc,0x2b]
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vcvtb.f64.f16 d3, s1
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@ CHECK-V81M: vcvtb.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0x60,0x3b]
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vcvtb.f16.f64 s4, d1
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@ CHECK-V81M: vcvtb.f16.f64 s4, d1 @ encoding: [0xb3,0xee,0x41,0x2b]
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it ge
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vcvttge.f64.f16 d3, s1
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@ CHECK-V81M: vcvttge.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
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it gt
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vcvttgt.f16.f64 s5, d12
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@ CHECK-V81M: vcvttgt.f16.f64 s5, d12 @ encoding: [0xf3,0xee,0xcc,0x2b]
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it eq
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vcvtbeq.f64.f16 d3, s1
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@ CHECK-V81M: vcvtbeq.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0x60,0x3b]
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it lt
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vcvtblt.f16.f64 s4, d1
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@ CHECK-V81M: vcvtblt.f16.f64 s4, d1 @ encoding: [0xb3,0xee,0x41,0x2b]
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@ VCVT{A,N,P,M}
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vcvta.s32.f32 s2, s3
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@ CHECK-V81M: vcvta.s32.f32 s2, s3 @ encoding: [0xbc,0xfe,0xe1,0x1a]
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vcvta.s32.f64 s2, d3
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@ CHECK-V81M: vcvta.s32.f64 s2, d3 @ encoding: [0xbc,0xfe,0xc3,0x1b]
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vcvtn.s32.f32 s6, s23
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@ CHECK-V81M: vcvtn.s32.f32 s6, s23 @ encoding: [0xbd,0xfe,0xeb,0x3a]
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vcvtn.s32.f64 s6, d7
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@ CHECK-V81M: vcvtn.s32.f64 s6, d7 @ encoding: [0xbd,0xfe,0xc7,0x3b]
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vcvtp.s32.f32 s0, s4
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@ CHECK-V81M: vcvtp.s32.f32 s0, s4 @ encoding: [0xbe,0xfe,0xc2,0x0a]
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vcvtp.s32.f64 s0, d4
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@ CHECK-V81M: vcvtp.s32.f64 s0, d4 @ encoding: [0xbe,0xfe,0xc4,0x0b]
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vcvtm.s32.f32 s17, s8
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@ CHECK-V81M: vcvtm.s32.f32 s17, s8 @ encoding: [0xff,0xfe,0xc4,0x8a]
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vcvtm.s32.f64 s17, d8
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@ CHECK-V81M: vcvtm.s32.f64 s17, d8 @ encoding: [0xff,0xfe,0xc8,0x8b]
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vcvta.u32.f32 s2, s3
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@ CHECK-V81M: vcvta.u32.f32 s2, s3 @ encoding: [0xbc,0xfe,0x61,0x1a]
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vcvta.u32.f64 s2, d3
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@ CHECK-V81M: vcvta.u32.f64 s2, d3 @ encoding: [0xbc,0xfe,0x43,0x1b]
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vcvtn.u32.f32 s6, s23
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@ CHECK-V81M: vcvtn.u32.f32 s6, s23 @ encoding: [0xbd,0xfe,0x6b,0x3a]
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vcvtn.u32.f64 s6, d7
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@ CHECK-V81M: vcvtn.u32.f64 s6, d7 @ encoding: [0xbd,0xfe,0x47,0x3b]
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vcvtp.u32.f32 s0, s4
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@ CHECK-V81M: vcvtp.u32.f32 s0, s4 @ encoding: [0xbe,0xfe,0x42,0x0a]
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vcvtp.u32.f64 s0, d4
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@ CHECK-V81M: vcvtp.u32.f64 s0, d4 @ encoding: [0xbe,0xfe,0x44,0x0b]
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vcvtm.u32.f32 s17, s8
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@ CHECK-V81M: vcvtm.u32.f32 s17, s8 @ encoding: [0xff,0xfe,0x44,0x8a]
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vcvtm.u32.f64 s17, d8
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@ CHECK-V81M: vcvtm.u32.f64 s17, d8 @ encoding: [0xff,0xfe,0x48,0x8b]
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@ VSEL
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vselge.f32 s4, s1, s23
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@ CHECK-V81M: vselge.f32 s4, s1, s23 @ encoding: [0x20,0xfe,0xab,0x2a]
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vselge.f64 d0, d1, d3
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@ CHECK-V81M: vselge.f64 d0, d1, d3 @ encoding: [0x21,0xfe,0x03,0x0b]
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vselgt.f32 s0, s1, s0
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@ CHECK-V81M: vselgt.f32 s0, s1, s0 @ encoding: [0x30,0xfe,0x80,0x0a]
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vselgt.f64 d5, d10, d11
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@ CHECK-V81M: vselgt.f64 d5, d10, d11 @ encoding: [0x3a,0xfe,0x0b,0x5b]
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vseleq.f32 s30, s28, s23
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@ CHECK-V81M: vseleq.f32 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xfa]
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vseleq.f64 d2, d4, d8
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@ CHECK-V81M: vseleq.f64 d2, d4, d8 @ encoding: [0x04,0xfe,0x08,0x2b]
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vselvs.f32 s21, s16, s14
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@ CHECK-V81M: vselvs.f32 s21, s16, s14 @ encoding: [0x58,0xfe,0x07,0xaa]
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vselvs.f64 d0, d1, d15
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@ CHECK-V81M: vselvs.f64 d0, d1, d15 @ encoding: [0x11,0xfe,0x0f,0x0b]
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@ VMAXNM / VMINNM
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vmaxnm.f32 s5, s12, s0
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@ CHECK-V81M: vmaxnm.f32 s5, s12, s0 @ encoding: [0xc6,0xfe,0x00,0x2a]
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vmaxnm.f64 d5, d14, d15
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@ CHECK-V81M: vmaxnm.f64 d5, d14, d15 @ encoding: [0x8e,0xfe,0x0f,0x5b]
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vminnm.f32 s0, s0, s12
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@ CHECK-V81M: vminnm.f32 s0, s0, s12 @ encoding: [0x80,0xfe,0x46,0x0a]
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vminnm.f64 d4, d6, d9
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@ CHECK-V81M: vminnm.f64 d4, d6, d9 @ encoding: [0x86,0xfe,0x49,0x4b]
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@ VRINT{Z,R,X}
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it ge
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vrintzge.f64 d3, d12
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@ CHECK-V81M: vrintzge.f64 d3, d12 @ encoding: [0xb6,0xee,0xcc,0x3b]
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vrintz.f32 s3, s24
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@ CHECK-V81M: vrintz.f32 s3, s24 @ encoding: [0xf6,0xee,0xcc,0x1a]
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it lt
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vrintrlt.f64 d5, d0
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@ CHECK-V81M: vrintrlt.f64 d5, d0 @ encoding: [0xb6,0xee,0x40,0x5b]
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vrintr.f32 s0, s9
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@ CHECK-V81M: vrintr.f32 s0, s9 @ encoding: [0xb6,0xee,0x64,0x0a]
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it eq
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vrintxeq.f64 d14, d15
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@ CHECK-V81M: vrintxeq.f64 d14, d15 @ encoding: [0xb7,0xee,0x4f,0xeb]
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it vs
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vrintxvs.f32 s10, s14
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@ CHECK-V81M: vrintxvs.f32 s10, s14 @ encoding: [0xb7,0xee,0x47,0x5a]
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@ VRINT{A,N,P,M}
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vrinta.f64 d3, d4
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@ CHECK-V81M: vrinta.f64 d3, d4 @ encoding: [0xb8,0xfe,0x44,0x3b]
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vrinta.f32 s12, s1
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@ CHECK-V81M: vrinta.f32 s12, s1 @ encoding: [0xb8,0xfe,0x60,0x6a]
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vrintn.f64 d3, d4
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@ CHECK-V81M: vrintn.f64 d3, d4 @ encoding: [0xb9,0xfe,0x44,0x3b]
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vrintn.f32 s12, s1
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@ CHECK-V81M: vrintn.f32 s12, s1 @ encoding: [0xb9,0xfe,0x60,0x6a]
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vrintp.f64 d3, d4
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@ CHECK-V81M: vrintp.f64 d3, d4 @ encoding: [0xba,0xfe,0x44,0x3b]
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vrintp.f32 s12, s1
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@ CHECK-V81M: vrintp.f32 s12, s1 @ encoding: [0xba,0xfe,0x60,0x6a]
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vrintm.f64 d3, d4
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@ CHECK-V81M: vrintm.f64 d3, d4 @ encoding: [0xbb,0xfe,0x44,0x3b]
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vrintm.f32 s12, s1
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@ CHECK-V81M: vrintm.f32 s12, s1 @ encoding: [0xbb,0xfe,0x60,0x6a]
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@ MVFR2
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vmrs sp, mvfr2
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@ CHECK-V81M: vmrs sp, mvfr2 @ encoding: [0xf5,0xee,0x10,0xda]
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