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e9d4f961f1
This commit prepares the way to start adding the main collection of
MVE instructions, which operate on the 128-bit vector registers.
The most obvious thing that's needed, and the simplest, is to add the
MQPR register class, which is like the existing QPR except that it has
fewer registers in it.
The more complicated part: MVE defines a system of vector predication,
in which instructions operating on 128-bit vector registers can be
constrained to operate on only a subset of the lanes, using a system
of prefix instructions similar to the existing Thumb IT, in that you
have one prefix instruction which designates up to 4 following
instructions as subject to predication, and within that sequence, the
predicate can be inverted by means of T/E suffixes ('Then' / 'Else').
To support instructions of this type, we've added two new Tablegen
classes `vpred_n` and `vpred_r` for standard clusters of MC operands
to add to a predicated instruction. Both include a flag indicating how
the instruction is predicated at all (options are T, E and 'not
predicated'), and an input register field for the register controlling
the set of active lanes. They differ from each other in that `vpred_r`
also includes an input operand for the previous value of the output
register, for instructions that leave inactive lanes unchanged.
`vpred_n` lacks that extra operand; it will be used for instructions
that don't preserve inactive lanes in their output register (either
because inactive lanes are zeroed, as the MVE load instructions do, or
because the output register isn't a vector at all).
This commit also adds the family of prefix instructions themselves
(VPT / VPST), and all the machinery needed to work with them in
assembly and disassembly (e.g. generating the 't' and 'e' mnemonic
suffixes on disassembled instructions within a predicated block)
I've added a couple of demo instructions that derive from the new
Tablegen base classes and use those two operand clusters. The bulk of
the vector instructions will come in followup commits small enough to
be manageable. (One exception is that I've added the full version of
`isMnemonicVPTPredicable` in the AsmParser, because it seemed
pointless to carefully split it up.)
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62669
llvm-svn: 363258
58 lines
2.1 KiB
ArmAsm
58 lines
2.1 KiB
ArmAsm
# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \
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# RUN: | FileCheck --check-prefix=CHECK-NOFP %s
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# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
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# RUN: | FileCheck --check-prefix=CHECK %s
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# RUN: FileCheck --check-prefix=ERROR < %t %s
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: VPT predicated instructions must be in VPT block
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vabavt.s32 lr, q1, q3
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: VPT predicated instructions must be in VPT block
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vabave.u8 r12, q1, q3
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# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: instructions in IT block must be predicable
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it eq
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vabav.s16 lr, q1, q3
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# CHECK: vpteee.i8 eq, q0, q1 @ encoding: [0x41,0xfe,0x02,0x2f]
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# CHECK-NOFP: vpteee.i8 eq, q0, q1 @ encoding: [0x41,0xfe,0x02,0x2f]
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vpteee.i8 eq, q0, q1
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vabavt.s32 lr, q1, q3
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vabave.s32 lr, q1, q3
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vabave.s32 lr, q1, q3
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vabave.s32 lr, q1, q3
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# CHECK: vptttt.s32 gt, q0, q1 @ encoding: [0x21,0xfe,0x03,0x3f]
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# CHECK-NOFP: vptttt.s32 gt, q0, q1 @ encoding: [0x21,0xfe,0x03,0x3f]
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vptttt.s32 gt, q0, q1
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vabavt.u32 lr, q1, q3
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vabavt.s32 lr, q1, q3
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vabavt.s16 lr, q1, q3
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vabavt.s8 lr, q1, q3
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# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: instruction in VPT block must be predicable
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vpt.s8 le, q0, q1
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cinc lr, r2, lo
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# ----------------------------------------------------------------------
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# The following tests have to go last because of the NOFP-NOT checks inside the
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# VPT block.
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# CHECK: vptete.f16 ne, q0, q1 @ encoding: [0x71,0xfe,0x82,0xef]
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# CHECK-NOFP-NOT: vptete.f16 ne, q0, q1 @ encoding: [0x71,0xfe,0x82,0xef]
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vptete.f16 ne, q0, q1
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vabavt.s32 lr, q1, q3
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vabave.u32 lr, q1, q3
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vabavt.s32 lr, q1, q3
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vabave.s16 lr, q1, q3
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: VPT predicated instructions must be in VPT block
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vabavt.s32 lr, q1, q3
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# CHECK: vpte.i8 eq, q0, q0
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# CHECK: vmaxnmt.f16 q1, q6, q2 @ encoding: [0x1c,0xff,0x54,0x2f]
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# CHECK-NOFP-NOT: vmaxnmt.f16 q1, q6, q2 @ encoding: [0x1c,0xff,0x54,0x2f]
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# CHECK-NOFP-NOT: vmaxnme.f16 q1, q6, q2 @ encoding: [0x1c,0xff,0x54,0x2f]
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vpte.i8 eq, q0, q0
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vmaxnmt.f16 q1, q6, q2
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vmaxnme.f16 q1, q6, q2
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