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216a9fc9a1
Summary: The symbols use the processor-specific SHN_AMDGPU_LDS section index introduced with a previous change. The linker is then expected to resolve relocations, which are also emitted. Initially disabled for HSA and PAL environments until they have caught up in terms of linker and runtime loader. Some notes: - The llvm.amdgcn.groupstaticsize intrinsics can no longer be lowered to a constant at compile times, which means some tests can no longer be applied. The current "solution" is a terrible hack, but the intrinsic isn't used by Mesa, so we can keep it for now. - We no longer know the full LDS size per kernel at compile time, which means that we can no longer generate a relevant error message at compile time. It would be possible to add a check for the size of individual variables, but ultimately the linker will have to perform the final check. Change-Id: If66dbf33fccfbf3609aefefa2558ac0850d42275 Reviewers: arsenm, rampitec, t-tye, b-sumner, jsjodin Subscribers: qcolombet, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61494 llvm-svn: 364297
38 lines
1.6 KiB
LLVM
38 lines
1.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
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; This is used to crash in LiveIntervalAnalysis via SILoadStoreOptimizer
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; while fixing up the merge of two ds_write instructions.
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@tess_lds = external addrspace(3) global [8192 x i32]
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; CHECK-LABEL: {{^}}main:
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; CHECK: ds_write_b32
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; CHECK: ds_write_b32
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; CHECK: v_mov_b32_e32 v1, v0
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; CHECK: tbuffer_store_format_xyzw v[0:3],
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define amdgpu_vs void @main(i32 inreg %arg) {
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main_body:
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%tmp = load float, float addrspace(3)* undef, align 4
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%tmp1 = load float, float addrspace(3)* undef, align 4
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store float %tmp, float addrspace(3)* null, align 4
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%tmp2 = bitcast float %tmp to i32
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%tmp3 = add nuw nsw i32 0, 1
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = getelementptr [8192 x i32], [8192 x i32] addrspace(3)* @tess_lds, i64 0, i64 %tmp4
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%tmp6 = bitcast i32 addrspace(3)* %tmp5 to float addrspace(3)*
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store float %tmp1, float addrspace(3)* %tmp6, align 4
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%tmp7 = bitcast float %tmp1 to i32
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%tmp8 = insertelement <4 x i32> undef, i32 %tmp2, i32 0
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%tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp7, i32 1
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%tmp10 = insertelement <4 x i32> %tmp9, i32 undef, i32 2
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%tmp11 = insertelement <4 x i32> %tmp10, i32 undef, i32 3
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call void @llvm.amdgcn.tbuffer.store.v4i32(<4 x i32> %tmp11, <4 x i32> undef, i32 undef, i32 0, i32 %arg, i32 0, i32 14, i32 4, i1 1, i1 1)
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ret void
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}
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; Function Attrs: nounwind
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declare void @llvm.amdgcn.tbuffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) #0
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attributes #0 = { nounwind }
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