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22ba99e3f8
"Divergence driven ISel. Assign register class for cross block values
according to the divergence."
that discovered the design flaw leading to several issues that
required to be solved before.
This change reverts AMDGPU specific changes and keeps common part
unaffected.
llvm-svn: 362749
46 lines
1.5 KiB
LLVM
46 lines
1.5 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -amdgpu-dce-in-ra=0 -o - %s | FileCheck %s
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; Don't crash when the use of an undefined value is only detected by the
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; register coalescer because it is hidden with subregister insert/extract.
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target triple="amdgcn--"
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; CHECK-LABEL: foobar:
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; CHECK: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
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; CHECK-NEXT: v_mbcnt_lo_u32_b32_e64
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; CHECK-NEXT: s_mov_b32 s2, -1
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v1, s5
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; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; CHECK: BB0_1:
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; CHECK-NEXT: ; kill: def $vgpr0_vgpr1 killed $sgpr4_sgpr5 killed $exec
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; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: BB0_2:
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; CHECK: s_or_b64 exec, exec, s[4:5]
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; CHECK-NEXT: s_mov_b32 s3, 0xf000
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; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], 0
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; CHECK-NEXT: s_endpgm
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define amdgpu_kernel void @foobar(float %a0, float %a1, float addrspace(1)* %out) nounwind {
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entry:
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%v0 = insertelement <4 x float> undef, float %a0, i32 0
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%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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%cnd = icmp eq i32 %tid, 0
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br i1 %cnd, label %ift, label %ife
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ift:
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%v1 = insertelement <4 x float> undef, float %a1, i32 0
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br label %ife
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ife:
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%val = phi <4 x float> [ %v1, %ift ], [ %v0, %entry ]
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%v2 = extractelement <4 x float> %val, i32 1
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store float %v2, float addrspace(1)* %out, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
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attributes #0 = { nounwind readnone }
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