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9af311f3de
Add the Lanai backend to lib/Target. General Lanai backend discussion on llvm-dev thread "[RFC] Lanai backend" (http://lists.llvm.org/pipermail/llvm-dev/2016-February/095118.html). Differential Revision: http://reviews.llvm.org/D17011 llvm-svn: 264578
97 lines
2.1 KiB
LLVM
97 lines
2.1 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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; Test that basic 32-bit integer comparison operations assemble as expected.
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target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
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target triple = "lanai"
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; CHECK-LABEL: eq_i32:
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; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0
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; CHECK-NEXT: seq
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define i32 @eq_i32(i32 %x, i32 %y) {
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%a = icmp eq i32 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: ne_i32:
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; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0
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; CHECK-NEXT: sne
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define i32 @ne_i32(i32 %x, i32 %y) {
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%a = icmp ne i32 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: slt_i32:
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; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0
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; CHECK-NEXT: slt
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define i32 @slt_i32(i32 %x, i32 %y) {
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%a = icmp slt i32 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: sle_i32:
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; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0
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; CHECK-NEXT: sle
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define i32 @sle_i32(i32 %x, i32 %y) {
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%a = icmp sle i32 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: ult_i32:
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; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0
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; CHECK-NEXT: sult
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define i32 @ult_i32(i32 %x, i32 %y) {
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%a = icmp ult i32 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: ule_i32:
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; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0
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; CHECK-NEXT: sule
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define i32 @ule_i32(i32 %x, i32 %y) {
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%a = icmp ule i32 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: sgt_i32:
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; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0
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; CHECK-NEXT: sgt
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define i32 @sgt_i32(i32 %x, i32 %y) {
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%a = icmp sgt i32 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: sge_i32:
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; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0
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; CHECK-NEXT: sge
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define i32 @sge_i32(i32 %x, i32 %y) {
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%a = icmp sge i32 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: ugt_i32:
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; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0
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; CHECK-NEXT: sugt
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define i32 @ugt_i32(i32 %x, i32 %y) {
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%a = icmp ugt i32 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: uge_i32:
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; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0
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; CHECK-NEXT: suge
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define i32 @uge_i32(i32 %x, i32 %y) {
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%a = icmp uge i32 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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