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46d19bc0c7
If the arch is P8, we will select XFLOAD to load the floating point, and then, expand it to vsx and non-vsx X-form instruction post RA. This patch is trying to convert the X-form to D-form if it meets the requirement that one operand of the x-form inst is the special Zero register, and another operand fed by add inst. i.e. y = add imm, reg LFDX. 0, y --> LFD imm(reg) Reviewers: Nemanjai Differential Revision: https://reviews.llvm.org/D49007 llvm-svn: 340149
47 lines
2.1 KiB
LLVM
47 lines
2.1 KiB
LLVM
; RUN: llc -O3 -ppc-late-peephole=false -o - %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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%class1 = type { %union1 }
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%union1 = type { i64, [24 x i8] }
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%class2 = type { %class3 }
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%class3 = type { %class4 }
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%class4 = type { %class5, i64, %union.anon }
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%class5 = type { i8* }
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%union.anon = type { i64, [8 x i8] }
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@ext = external global %"class1", align 8
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; We can't select lxv for this because even though we're accessing an offset of
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; 16 from the stack slot, the stack slot is only guaranteed to be 8-byte
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; aligned. When the frame is finalized it is converted to lxv (frame-reg) +
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; (offset + 16). Because offset isn't guaranteed to be 16-byte aligned, we may
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; end up needing to translate the lxv instruction to lxvx
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; CHECK-LABEL: unaligned_slot:
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; CHECK-NOT: lxv {{[0-9]+}}, {{[-0-9]+}}({{[0-9]+}})
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; CHECK: blr
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define void @unaligned_slot() #0 {
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%1 = alloca %class2, align 8
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%2 = getelementptr inbounds %class2, %class2* %1, i64 0, i32 0, i32 0, i32 2
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%3 = bitcast %union.anon* %2 to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 nonnull getelementptr inbounds (%class1, %class1* @ext, i64 0, i32 0, i32 1, i64 8), i8* align 8 nonnull %3, i64 16, i1 false) #2
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ret void
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}
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; CHECK-LABEL: aligned_slot:
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; CHECK: lxv {{[0-9]+}}, {{[-0-9]+}}({{[0-9]+}})
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; CHECK: blr
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define void @aligned_slot() #0 {
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%1 = alloca %class2, align 16
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%2 = getelementptr inbounds %class2, %class2* %1, i64 0, i32 0, i32 0, i32 2
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%3 = bitcast %union.anon* %2 to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 nonnull getelementptr inbounds (%class1, %class1* @ext, i64 0, i32 0, i32 1, i64 8), i8* align 8 nonnull %3, i64 16, i1 false) #2
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ret void
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}
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; Function Attrs: argmemonly nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) #1
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attributes #0 = { nounwind "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { argmemonly nounwind }
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attributes #2 = { nounwind }
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