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46d19bc0c7
If the arch is P8, we will select XFLOAD to load the floating point, and then, expand it to vsx and non-vsx X-form instruction post RA. This patch is trying to convert the X-form to D-form if it meets the requirement that one operand of the x-form inst is the special Zero register, and another operand fed by add inst. i.e. y = add imm, reg LFDX. 0, y --> LFD imm(reg) Reviewers: Nemanjai Differential Revision: https://reviews.llvm.org/D49007 llvm-svn: 340149
36 lines
1.4 KiB
LLVM
36 lines
1.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O1 -code-model=medium \
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; RUN: -mattr=-vsx < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O1 -code-model=medium \
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; RUN: -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O1 -code-model=medium < %s | \
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; RUN: FileCheck -check-prefix=CHECK-P9 %s
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; Test peephole optimization for medium code model (32-bit TOC offsets)
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; for loading a value from the constant pool (TOC-relative).
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define double @test_double_const() nounwind {
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entry:
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ret double 0x3F4FD4920B498CF0
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}
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; CHECK: [[VAR:[a-z0-9A-Z_.]+]]:
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; CHECK: .quad 4562098671269285104
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; CHECK-LABEL: test_double_const:
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; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
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; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
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; CHECK-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
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; CHECK-VSX: .quad 4562098671269285104
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; CHECK-VSX-LABEL: test_double_const:
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; CHECK-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
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; CHECK-VSX: lfd {{[0-9]+}}, [[VAR]]@toc@l({{[0-9]+}})
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; CHECK-P9: [[VAR:[a-z0-9A-Z_.]+]]:
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; CHECK-P9: .quad 4562098671269285104
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; CHECK-P9-LABEL: test_double_const:
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; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
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; CHECK-P9: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
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