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f60a29f8fa
We fail to canonicalize IR this way (prefer 'not' ops to arbitrary 'xor'), but that would not matter without this patch because DAGCombiner was reversing that transform. I think we need this transform in the backend regardless of what happens in IR to catch cases where the shift-xor is formed late from GEP or other ops. https://rise4fun.com/Alive/NC1 Name: shl Pre: (-1 << C2) == C1 %shl = shl i8 %x, C2 %r = xor i8 %shl, C1 => %not = xor i8 %x, -1 %r = shl i8 %not, C2 Name: shr Pre: (-1 u>> C2) == C1 %sh = lshr i8 %x, C2 %r = xor i8 %sh, C1 => %not = xor i8 %x, -1 %r = lshr i8 %not, C2 https://bugs.llvm.org/show_bug.cgi?id=39657 llvm-svn: 347478
113 lines
3.1 KiB
LLVM
113 lines
3.1 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i32 0, align 4
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) {
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entry:
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%cmp = icmp uge i32 %a, %b
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%conv1 = zext i1 %cmp to i64
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ret i64 %conv1
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; CHECK-LABEL: test_llgeui:
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; CHECK: sub [[REG1:r[0-9]+]], r3, r4
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; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
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; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llgeui_sext(i32 zeroext %a, i32 zeroext %b) {
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entry:
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%cmp = icmp uge i32 %a, %b
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%conv1 = sext i1 %cmp to i64
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ret i64 %conv1
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; CHECK-LABEL: @test_llgeui_sext
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; CHECK: sub [[REG1:r[0-9]+]], r3, r4
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
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; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llgeui_z(i32 zeroext %a) {
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entry:
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%cmp = icmp uge i32 %a, 0
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%conv1 = zext i1 %cmp to i64
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ret i64 %conv1
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; CHECK-LABEL: @test_llgeui_z
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; CHECK: li r3, 1
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llgeui_sext_z(i32 zeroext %a) {
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entry:
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%cmp = icmp uge i32 %a, 0
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%conv1 = sext i1 %cmp to i64
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ret i64 %conv1
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; CHECK-LABEL: @test_llgeui_sext_z
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; CHECK: li r3, -1
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) {
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entry:
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%cmp = icmp uge i32 %a, %b
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @glob
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ret void
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; CHECK_LABEL: test_igeuc_store:
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; CHECK: sub [[REG1:r[0-9]+]], r3, r4
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; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
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; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
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entry:
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%cmp = icmp uge i32 %a, %b
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%sub = sext i1 %cmp to i32
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store i32 %sub, i32* @glob
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ret void
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; CHECK-LABEL: @test_llgeui_sext_store
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; CHECK: sub [[REG1:r[0-9]+]], r3, r4
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; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
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; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
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; CHECK: stw [[REG3]]
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_llgeui_z_store(i32 zeroext %a) {
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entry:
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%cmp = icmp uge i32 %a, 0
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%sub = zext i1 %cmp to i32
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store i32 %sub, i32* @glob
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ret void
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; CHECK-LABEL: @test_llgeui_z_store
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; CHECK: li [[REG1:r[0-9]+]], 1
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; CHECK: stw [[REG1]]
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_llgeui_sext_z_store(i32 zeroext %a) {
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entry:
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%cmp = icmp uge i32 %a, 0
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%sub = sext i1 %cmp to i32
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store i32 %sub, i32* @glob
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ret void
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; CHECK-LABEL: @test_llgeui_sext_z_store
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; CHECK: li [[REG1:r[0-9]+]], -1
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; CHECK: stw [[REG1]]
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; CHECK: blr
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}
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