mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
30264d4391
As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
61 lines
2.0 KiB
LLVM
61 lines
2.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
|
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
|
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
|
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
|
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
|
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
|
|
|
@glob = common local_unnamed_addr global i8 0, align 1
|
|
|
|
; Function Attrs: norecurse nounwind readnone
|
|
define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) {
|
|
; CHECK-LABEL: test_llltuc:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
|
|
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%cmp = icmp ult i8 %a, %b
|
|
%conv3 = zext i1 %cmp to i64
|
|
ret i64 %conv3
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind readnone
|
|
define i64 @test_llltuc_sext(i8 zeroext %a, i8 zeroext %b) {
|
|
; CHECK-LABEL: test_llltuc_sext:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
|
|
; CHECK-NEXT: sradi r3, [[REG]], 63
|
|
; CHECK-NEXT: blr
|
|
entry:
|
|
%cmp = icmp ult i8 %a, %b
|
|
%conv3 = sext i1 %cmp to i64
|
|
ret i64 %conv3
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) {
|
|
; CHECK-LABEL: test_llltuc_store:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK: sub [[REG:r[2-9]+]], r3, r4
|
|
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
|
|
entry:
|
|
%cmp = icmp ult i8 %a, %b
|
|
%conv3 = zext i1 %cmp to i8
|
|
store i8 %conv3, i8* @glob, align 1
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
|
|
; CHECK-LABEL: test_llltuc_sext_store:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK: sub [[REG:r[0-9]+]], r3, r4
|
|
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
|
|
entry:
|
|
%cmp = icmp ult i8 %a, %b
|
|
%conv3 = sext i1 %cmp to i8
|
|
store i8 %conv3, i8* @glob, align 1
|
|
ret void
|
|
}
|