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https://github.com/RPCS3/llvm-mirror.git
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edd36f6e4c
Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
109 lines
3.2 KiB
LLVM
109 lines
3.2 KiB
LLVM
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc --relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i32 0, align 4
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: test_llltui:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: clrldi
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; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
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; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ult i32 %a, %b
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%conv1 = zext i1 %cmp to i64
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ret i64 %conv1
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: test_llltui_sext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
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; CHECK-NEXT: sradi r3, [[REG]], 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ult i32 %a, %b
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%conv1 = sext i1 %cmp to i64
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ret i64 %conv1
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llltui_z(i32 zeroext %a) {
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; CHECK-LABEL: test_llltui_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: blr
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entry:
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ret i64 0
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llltui_sext_z(i32 zeroext %a) {
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; CHECK-LABEL: test_llltui_sext_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: blr
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entry:
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ret i64 0
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}
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; Function Attrs: norecurse nounwind
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define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: test_llltui_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: clrldi
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; CHECK: sub [[REG:r[2-9]+]], r3, r4
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; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
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entry:
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%cmp = icmp ult i32 %a, %b
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @glob, align 4
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: test_llltui_sext_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: clrldi
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; CHECK: sub [[REG:r[0-9]+]], r3, r4
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; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
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entry:
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%cmp = icmp ult i32 %a, %b
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%sub = sext i1 %cmp to i32
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store i32 %sub, i32* @glob, align 4
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_llltui_z_store(i32 zeroext %a) {
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; CHECK-LABEL: test_llltui_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK: li [[REG:r[0-9]+]], 0
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; CHECK: stw [[REG]], 0(r3)
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; CHECK-NEXT: blr
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entry:
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store i32 0, i32* @glob, align 4
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_llltui_sext_z_store(i32 zeroext %a) {
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; CHECK-LABEL: test_llltui_sext_z_store:
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; CHECK: # %bb.0: # %entry
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; CHECK: li [[REG:r[0-9]+]], 0
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; CHECK: stw [[REG]], 0(r3)
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; CHECK-NEXT: blr
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entry:
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store i32 0, i32* @glob, align 4
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ret void
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}
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