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a1467f07ff
When we need to do an fp->int conversion using x87 instructions, we need to temporarily change the rounding mode to 0b11 and perform a store. To do this we save the old value of the fpcw to the stack, then set the fpcw to 0xc7f, do the store, then restore fpcw. But the 0xc7f value forces the exception mask bits 1. While this is what they would be in the default FP environment, as we move to support changing the FP environments, we shouldn't make this assumption. This patch changes the code to explicitly OR 0xc00 with the old value so that only the rounding mode is changed. Unfortunately, this requires two stack temporaries instead of one. One to hold the old value and one to hold the new value. Without two stack temporaries we would need an additional GPR. We already need one to do the OR operation in. This is similar to what gcc and icc do for this operation. Though they are both better at reusing the stack temporaries when there are multiple truncates in a function(or at least in a basic block) Differential Revision: https://reviews.llvm.org/D57788 llvm-svn: 354178
44 lines
1.7 KiB
LLVM
44 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux -mcpu=x86-64 | FileCheck %s
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define x86_fp80 @rem_pio2l_min(x86_fp80 %z) {
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; CHECK-LABEL: rem_pio2l_min:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fnstcw -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: orl $3072, %eax # imm = 0xC00
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; CHECK-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: fistl -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: fisubl -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: flds {{.*}}(%rip)
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; CHECK-NEXT: fmul %st, %st(1)
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; CHECK-NEXT: fnstcw -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: orl $3072, %eax # imm = 0xC00
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; CHECK-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: fxch %st(1)
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; CHECK-NEXT: fistl -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: fisubl -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: fmulp %st, %st(1)
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; CHECK-NEXT: retq
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entry:
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%conv = fptosi x86_fp80 %z to i32
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%conv1 = sitofp i32 %conv to x86_fp80
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%sub = fsub x86_fp80 %z, %conv1
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%mul = fmul x86_fp80 %sub, 0xK40178000000000000000
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%conv2 = fptosi x86_fp80 %mul to i32
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%conv3 = sitofp i32 %conv2 to x86_fp80
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%sub4 = fsub x86_fp80 %mul, %conv3
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%mul5 = fmul x86_fp80 %sub4, 0xK40178000000000000000
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ret x86_fp80 %mul5
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}
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